61–70 of 84 posts
little nitpick: it's "combinational circuits", not "combinatorial" (that's whole another part of math)
Do you have a reference for that? I'm genuinely curious since both terms are used in literature.
Your article has reduced my fear (and also, you mentioned the price of that Tiny FPGA board; at that price point, I don't mind too much if the magic smoke gets out).
The problem of FPGAs is their proprietary nature, and Verilog/VHDL are far from the best languages. Gladly there is a number of open-source projects aiming to close this gap - Yosys[1], SymbiFlow[2], Chisel3[3]/FIRRTL[4]. Some time ago I suggested[5] different open source projects should unite and reuse the common intermediate language, akin to LLVM in many software development and analysis tools. From my point of vi…
Now that we have some nice FPGA's we can use I think this is the next biggest hurdle.
Earlier quoted context omitted.
Nice work. FPGA design appears to be very similar to GPU shader programming. First time I've read anything about FPGA design that connected. Usually FPGA stories get lost in data flow jargon and I learn nothing.
There is no programming in FPGA at all. You describe your hardware using hardware description languages like VHDL or Verilog.
The problem of FPGAs is their proprietary nature, and Verilog/VHDL are far from the best languages. Gladly there is a number of open-source projects aiming to close this gap - Yosys[1], SymbiFlow[2], Chisel3[3]/FIRRTL[4]. Some time ago I suggested[5] different open source projects should unite and reuse the common intermediate language, akin to LLVM in many software development and analysis tools. From my point of vi…
I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. What I am missing are 2 topics: timing analysis and debugging. Static timing analysis and proper timing constrains are crucial for functional design. No tool can differentiate without constrains a slow signal signal toggling LED every 10 seconds from DDR3 533 MHz differential c…
I think "Chipscope" is a Xilinx thing actually.
This is a pretty nice tutorial! My courses in FPGA design in school taught me a ton about 1) concurrency and 2) good state machine design. In modern backend web development these topics receive so little attention (from interviewing all the way to writing technical specs, I've rarely encountered these topics brought up explicitly) but are important. I was a bit hesitant for this guide to suggest using C++ since I ten…
Earlier quoted context omitted.
I disagree about for loops, you actually end up using these quite a lot in vhdl/verilog (with understanding about what logic you are going to end up with), if you want to do the same operation on multiple things: input [NUM_OF_MULTIPLIERS*32-1:0] a_in, input [NUM_OF_MULTIPLIERS*32-1:0] b_in, output [NUM_OF_MULTIPLIERS*64-1:0] mult_out reg [31:0] tmp_a, tmp_b; reg [63:0] tmp_mult; always @(*) begin mult_out = {(NUM_OF…
The key is that for loops are essentially pre-processor macros (like C) so they must have a fixed number of iterations known at compile time. So yes, you have a for loop, but it's very different to what you expect from a for loop in software.
I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. What I am missing are 2 topics: timing analysis and debugging. Static timing analysis and proper timing constrains are crucial for functional design. No tool can differentiate without constrains a slow signal signal toggling LED every 10 seconds from DDR3 533 MHz differential c…
> Intel has Chipscope I think "Chipscope" is a Xilinx thing actually.