CλaSH – From Haskell to Hardware

Ok, yeah sorry the docs other than the tutorial assume some familiarity with Haskell.

2. What do you mean by "verification IP"? It was that phrase that made me mention testbenches.

Basically, while CLaSH is hard coded to understand certain types such as the Signal type, almost all primitive function are just defined with Verilog/VHDL templates which it instantiates. One can write their own templates that work just the same way. So for any piece of CLaSH-compilable Haskell, you get VHDL/Verilog for free, and for any bit of piece of VHDL/Verilog, you can use it in CLaSH by writing some Haskell (with the same ports, and that hopefully does the same thing) and then telling CLaSH the Haskell is to be replaced with your Verilog/VHDL.

This is about as good bidirectional comparability as one can get. Automatic Verilog/VHDL -> CLaSH compilation would be an improvement, but I don't think it is possible: I'm not sure to what degree the semantics of Verilog/VHDL are formalized, and even if they are, there's no way the implementations all respect those semantics.

The testbench functions are just templated like any other primitive function.

1. UnsafeSynchronizer "casts" one signal to another -- it's compiled to a plain net in Verilog/VHDL. At each output cycle, n, it looks at the round(n*fin/fout) input cycle and give it that value.

Obviously this is unsafe because, as you say, in the real world the problem is asynchronous. You don't know the exact frequency ratios and phase differences, nor are they constant, and even if you did you'd get subtle timing errors with an incoming value that doesn't change on the clock edge.

The trick is it is a pretty basic "black box" to augment CLaSH with, so proper synthesizers can be written in pure CLaSH. if that's not enough for some super-asynchronous synchronizer design, one can always fall back on writing their own black-box as described above.

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I don't think anyone imagines that CLaSH will be immediately understandable to someone who has never used Haskell. So no way does anyone expect the benefits will be immediately clear. So are you saying the restrictions I mention sound too onerous, or are you saying "I dunno, it looks weird"?

If the former, that's perfectly acceptable, thank you for reading.

If the latter, I'm sorry but this is a pet peeve of mine--we get this a lot in the function programming community. Understand that we are claiming the benefits are worth the non-trivial learning curve. If it was so damn obvious, it couldn't offer much benefit over the status quo---people would have already switched en mass and it would be the status quo.

While C-esque cuteness looks nice, I agree such things are doomed to failure. The C model is easy enough to stand, but it's linearity, implicit state, and notion of control flow have nothing to do with the hardware---you can understand both models, but the compilation process is necessarily non-trivial and sufficiently "far from subjective" that many designs cannot be expressed at all, and many more must be expressed through very round about means.

Functional HDLs like CLaSH have a dead-simple structural compilation model, so while they may not understand every circuit, they can express it---the compiler is near subjective but not homomorphic counting these like this SR flip-flop:

  \ r s -> let q  = nor r q'
               q' = nor s q
           in (q, q')

This compiles to exactly what it looks like, but diverges (i.e. infinite loops) under Haskell's semantics.

Lastly here is a comparison of writing the same project twice (though the paper is done by the CLaSH designers) http://www.researchgate.net/profile/Jan_Kuper/publication/47...

Verification IP is reusable code created by verification engineers. E.g. Say the designers are developing a networking module. The verification engineers would build the verification IP to generate the network packets. They also build the monitors to check the network protocols. For any design under verification, there is a corresponding amount of verification providing stimulus and checking.

Check out: https://verificationacademy.com/verification-methodology-ref...

The reason I bring this up is: verification is the hard part of the HW workflow. The other similarly tough part is synthesis. Every single project I have been in, verification and synthesis are the toughest tasks that consumes the most team effort. Not design. When we plan projects, it all revolves around the verification task.

For every bus, every module and at various stages of SoC integration, we are writing verification code using System Verilog.

If you want to improve our tools, I would look at the verification/simulation or the synthesis side.

Latches are caught by the synthesis tools generally. Designers usually run a unconstrained synthesis as a matter of course to determine whether they have written junk.

As for the other bugs, I look forward to this new paradigm of spotting them early without verification effort.

Reasoning about transactions is already how verification works. It is transaction based. UVM is a library of SystemVerilog classes aimed at abstracting the verification to higher levels.

Check out: https://verificationacademy.com/verification-methodology-ref...

We build over these classes to create our test benches.