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Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

zeroasic.com

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Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#51

Post by nerpderp82 »

adapteva wrote: post #34
rowanG077 wrote: post #26

Earlier quoted context omitted.

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC. https://github.com/zeroasiccorp/wildebeest

FWIW, I was not confused and don't believe you need to clarify.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#52

Post by mrheosuper »

Aurornis wrote: post #44
st_goliath wrote: post #8

Earlier quoted context omitted.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

It's not that the official tools are the only way to work with parts. It's that they're the only vendor supported method of working with the parts. If you build your product with an unsupported toolset and something doesn't work, you need to be prepared to reproduce the issue in the vendor support toolchain if you want support. People coming from desktop and mobile development roll their eyes at this because they are…

>It's that they're the only vendor supported method of working with the parts

And it's because those engineers do not demand. "I Want something easy to use and has GUI, not some Terminal command line"

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#53

Post by rowanG077 »

nerpderp82 wrote: post #51
adapteva wrote: post #34

Earlier quoted context omitted.

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC. https://github.com/zeroasiccorp/wildebeest

FWIW, I was not confused and don't believe you need to clarify.

It was never about being confused.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#54

Post by Dylan16807 »

elsjaako wrote: post #28
rowanG077 wrote: post #26

Earlier quoted context omitted.

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I think we're reading the same article differently. They start out by describing all the work that has been done by other people to make open source synthesis possible. Then they say they've added some well known, industry standard optimizations to the existing open source tools. In addition, they made use of the abc tool in a way that maybe wasn't being done much before. My view is that if you think someone taking y…

> My view is that if you think someone taking your software, changing some parts, and releasing it under a different name (while still giving you credit in an about section) leaves a bad taste in your mouth, don't release your software with a permissive license. You are explicitly giving permission for someone to do this.

I don't agree that that kind of permission means you're not allowed to have a bad taste in your mouth. But even if I did agree, that argument only applies to the developer. You are not talking to the developer. We as third parties are fully allowed to complain.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#55

Post by dreamcompiler »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

It's that bad. FPGA designers on my team would routinely start a Vivado job and come back 8 hours later (because that's how long it typically took) and discover Vivado had crashed.

Vivado is expensive, bloated, buggy garbage.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#56

Post by dlcarrier »

adwn wrote: post #14
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

As much as I wish this would come true, there's little chance for a full, end-to-end open source toolchain for Xilinx or Altera FPGAs that's competitive with the vendor tools. The reason for this is that there's no publicly available documentation of the signal routing configuration or the bitstream format, which are required for the final two steps in the chain. I don't see the two market leaders releasing this info…

They seem to be pushing in that direction. Here's Altera's latest: https://github.com/OFS

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#57

Post by boatfloatgoat »

celegans25 wrote: post #37
boatfloatgoat wrote: post #32

will a smaller synthesis LUTs/logic depth result translate into smaller Map/P&R and higher fMax or not necessarily?

Often but not always. For most newer FPGAs, routing is the main source of delay on the critical path, not logic. So if the synthesis tool lowers the logic depth, but does so in a way that increases the distance the signal must travel on the chip, it likely won't help FMax. This can be caused by increased logic usage, if the synthesis tool must create significantly more LUTs to reduce the critical path. This may make…

[dead]

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#58

Post by [deleted] »

amluto wrote: post #39
someguydave wrote: post #38

Earlier quoted context omitted.

ah so this is misdirection - what they are really showcasing is their own new FPGA asic

They’re showcasing their open-source stack, built on existing tools, for their own FPGA. Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it woul…

[deleted]

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#59

Post by someguydave »

amluto wrote: post #39
someguydave wrote: post #38

Earlier quoted context omitted.

ah so this is misdirection - what they are really showcasing is their own new FPGA asic

They’re showcasing their open-source stack, built on existing tools, for their own FPGA. Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it woul…

in that case, such a company would be wise to include the fact that the "z1060" is a new CPU instead of failing to even mention what it is in their "new GCC port" press release page
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