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AMD's Turin: 5th Gen EPYC Launched

chipsandcheese.com

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Re: AMD's Turin: 5th Gen EPYC Launched

#51

Post by justmarc »

p1necone wrote: post #32
mistyvales wrote: post #17

Here I am running a 12 year old Dell PowerEdge with dual Xeons.. I wonder when the first gen Epyc servers will be cheap fodder on eBay.

1-3rd gen Epycs can be had super cheap, but the motherboards are expensive. Also not worth getting anything less than 3rd gen unless you're primarily buying them for the pcie lanes and ram capacity - a regular current gen consumer CPU with half - a quarter of the core count will outperform them in compute while consuming significantly less power.

Lots of great second hand hardware to be had on ebay. Even last gen used CPUs, as well as RAM, at much less than retail.

However when you end up building a server quite often the motherboard + case is the cheap stuff, the CPUs are second in cost and the biggest expense can be the RAM.

Re: AMD's Turin: 5th Gen EPYC Launched

#52

Post by justmarc »

Tuna-Fish wrote: post #49
Salgat wrote: post #35

Earlier quoted context omitted.

I wonder how this compares to the 7950x3d. So much cache and a high boost clock. https://www.amd.com/en/products/processors/server/epyc/9005-...

Great if you have 16 independent workloads, terrible for things that care about communication between threads. It has 16 CCD, each with only one thread enabled, latency between CCD is ~150ns.

Surprise surprise, not every tool is right for every job.

Re: AMD's Turin: 5th Gen EPYC Launched

#53

Post by justmarc »

elric wrote: post #25

At 1:11 in the video, there's a chart of the TDP (which I looked for in the text but couldn't find). At 125-500W, these things run very hot.

You just need one unit of these in dual socket config per room of your house, and you're sorted for the winter (if you live somewhere cold).

Re: AMD's Turin: 5th Gen EPYC Launched

#54

Post by tandr »

dragontamer wrote: post #5

ChipsAndCheese is one of the few new tech publications that really knows what they are talking about, especially with these deep dive benchmarks. With the loss of Anandtech, TechReport, HardCOP and other old technical sites, I'm glad to see a new publisher who can keep up with the older style stuff.

Did you mean to say HardOCP?

Re: AMD's Turin: 5th Gen EPYC Launched

#56

Post by kombine »

swarnie wrote: post #47
mistyvales wrote: post #17

Here I am running a 12 year old Dell PowerEdge with dual Xeons.. I wonder when the first gen Epyc servers will be cheap fodder on eBay.

Unsure about the Epyc chips but Ryzen 5 series kit was being given away on Amazon in the week... I snagged a 9 5950X for £242

Thanks for pointing out, it's still up there for £253 - I might consider upgrading my 8 core 5800X3D.

Re: AMD's Turin: 5th Gen EPYC Launched

#57

Post by dajonker »

phonon wrote: post #9
jeffbee wrote: post #6

The part with only 16 cores but 512MB L3 cache ... that must be for some specific workload.

Oracle can charge $40-$100k+ for EE including options per core (times .5)...and some workloads are very cache sensitive. So a high cache, high bandwidth, high frequency, high memory capacity 16 core CPU[1] (x2 socket) might be the best bang for their buck for that million dollar+ license. [1] https://www.amd.com/en/products/processors/server/epyc/9005-...

Surely that's a good reason for Oracle to increase their prices even more, leading to a cat-and-mouse game between CPU makers and software license sellers.

Re: AMD's Turin: 5th Gen EPYC Launched

#59

Post by zer00eyz »

justmarc wrote: post #50

Truly mind boggling scale. Twenty years ago we had just 1-2 cores per CPU, so we were lucky to have 4 cores in a dual socket server. A single server can now have almost 400 cores. Yes, we can have even more ARM cores but they don't perform as well as these do, at least for now.

700+ threads over 2 cores, can saturate 2 400gbe Nic's 500 wats per chip (less than 2 wats per thread)... All of that in a 2U package.... 20 years ago that would have been racks of gear.

Re: AMD's Turin: 5th Gen EPYC Launched

#60

Post by jsheard »

jeffbee wrote: post #6

The part with only 16 cores but 512MB L3 cache ... that must be for some specific workload.

The topology of that part is wild, it's physically the same silicon as the 128-core part but they've disabled all but one core on each compute chiplet. 112 cores are switched off to leave just 16 cores with as much cache as possible.

Inter-core latency will be rough since you'll always be hitting the relatively slow inter-chiplet bus, though.

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