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Raspberry Pi Pico does line rate 100M Ethernet

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Re: Raspberry Pi Pico does line rate 100M Ethernet

#51

Post by Hikikomori »

nsteel wrote: post #50
Hikikomori wrote: post #48

Earlier quoted context omitted.

What core routers uses imix?

Not sure what you mean, but an example of using imix to measure perf of a core router is Cisco 8000 series https://miercom.com/wp-content/uploads/2024/02/Performance-V...

That 8200 for example is capable of line rate at the smallest packet size so that imix marketing is kinda useless. When evaluating these kinds of devices this is what matters.

IMIX makes sense on devices that are not capable of small packet line rate like firewalls where bandwidth is much more costly and need to be sized appropriately.

Re: Raspberry Pi Pico does line rate 100M Ethernet

#52

Post by _flux »

vardump wrote: post #49
dlenski wrote: post #32

Usually I can grok the significance of almost any item on HN that catches my eye, but here I'm at a loss. Can someone explain why this matters? As far as I can tell, someone has figured out how to send Ethernet packets at a relatively high rate using hardware with very limited CPU. Cool, but what can you _do with that_? If the RPi Pico has the juice to run interesting network _application-level traffic_ at line rate…

RP2040/2350 are IO monsters. You could for example make a logic analyzer that transfers logic data through ethernet. This "very limited" microcontroller has two cores. Both of them can execute about 25 instructions per byte for generating "application-level traffic". You could definitely saturate a 100 Mbps connection with just one core.

Now that you mention it, I think I would like to see a logic analyzer that does just that. No buffering, just straight up shovel the data to a mac address, or even IP address, and be done with it (maybe lose a few frames here and there). Let the PC worry about what to do with it, like triggers etc.

Should be cheap, right? Though 1Gbit version might still be expensive..

Re: Raspberry Pi Pico does line rate 100M Ethernet

#53

Post by dmitrygr »

rscott2049 wrote: post #11
__michaelg wrote: post #4

> receive side uses a per-packet interrupt to finalize a received packet This has made much faster systems not being able to process packets at line speed. A classic was that standard Gigabit network cards and contemporary CPUs were not able to process VoIP packets (which are tiny) at line speed, while they could easily download files (which are basically MTU-sized packets) at line speed.

Fortunately, the receive ISR isn't cracking packets, just calculating a checksum and passing the packet on to LWIP. I wish there were two DMA sniffers, so that the checksum could be calculated by the DMA engine(s), as that's where a lot of processor time is spent (event with a table driven CRC routine).

You can do it using PIO. I did that for emulating memory stick slave on rp2040. One PIO SM plus two dma channels with chained descriptors. XOR is achieved using any io reg you don’t need, with 0x3000 offset (manual mentions this as the XOR alias)

Re: Raspberry Pi Pico does line rate 100M Ethernet

#54

Post by nsteel »

Hikikomori wrote: post #51
nsteel wrote: post #50

Earlier quoted context omitted.

Not sure what you mean, but an example of using imix to measure perf of a core router is Cisco 8000 series https://miercom.com/wp-content/uploads/2024/02/Performance-V...

That 8200 for example is capable of line rate at the smallest packet size so that imix marketing is kinda useless. When evaluating these kinds of devices this is what matters. IMIX makes sense on devices that are not capable of small packet line rate like firewalls where bandwidth is much more costly and need to be sized appropriately.

I don't have any Cisco core routers, not have I personally tested any, but that document I provided found their Q200 ASIC (in the 8000 series) required at least 170B frames to hit line rate:

> Both DUTs can achieve line rate performance on all ports with an NDR of 170 Bytes for the 88-LC0-36FH-M line card and 215 Bytes for 8201-32FH router. Same values were observed for both IPv4 and IPv6 traffic. This exceeds all real-life deployments requirements regardless of position in the network.

The 9000 series analysis reports something like 400B packets to hit line rate.

Fundamentally, everyone has to scale their internal bus width and clock rate to hit the headline numbers, always at the cost of small frame performance.

Re: Raspberry Pi Pico does line rate 100M Ethernet

#55

Post by sulandor »

crote wrote: post #10
__michaelg wrote: post #4

> receive side uses a per-packet interrupt to finalize a received packet This has made much faster systems not being able to process packets at line speed. A classic was that standard Gigabit network cards and contemporary CPUs were not able to process VoIP packets (which are tiny) at line speed, while they could easily download files (which are basically MTU-sized packets) at line speed.

Luckily the RP2040 has a dualcore CPU so one core can be dedicated entirely to receiving the interrupts, passing it to user code on the other core via a FIFO or whatever else you fancy.

almost

context switching between processors will reduce cache coherence and hence hits, but yea, it might be worth the tradeoff on busy systems

Re: Raspberry Pi Pico does line rate 100M Ethernet

#56

Post by MartijnBraam »

bangaladore wrote: post #24
molticrystal wrote: post #15

I see some examples that show this can be used as a lite http daemon. Is there enough room to have it control the ethernet port for another weaker or perhaps more powerful microcontroller? Can you combine multiple picos with one being the ethernet stack and another that modifies certain packets? Are there any other interesting things that can be done?

> Is there enough room to have it control the ethernet port for another weaker or perhaps more powerful microcontroller? Well there is a whole unused core and plenty of built in SRAM. Seems like a good way to have an open-source version of Wiznet chips [1]. It could support full protocol offloading like Wiznet's or a lower-level raw packet sender/receiver like the ENC424J600. [1] https://docs.wiznet.io/Product/iEther…

I just quickly tried to fit the whole rp2040+ethernet phy in the WIZ850io formfactor (mainly because I already used that module in some projects before) and have not yet been able to make it fit without using the more expensive jlcpcb features like burried vias. It would be very cool to have though since the W5500 really needs an update.

Re: Raspberry Pi Pico does line rate 100M Ethernet

#57

Post by Dylan16807 »

Hikikomori wrote: post #43
gbil wrote: post #41

Earlier quoted context omitted.

I'm many years away from such topics but I don't remember this being the case, moreover specs for net equipment was (is) on pps with the details stating usually 2-3 packet size categories. I'm interested on some reference on what you wrote

https://www.fmad.io/blog/what-is-10g-line-rate As the article calls it, the gold standard. If a device is capable of forwarding/switching packets at the smallest packet size line rate on all interfaces at the same time you don't have to think too much about its performance when designing your network. Haven't worked much with hardware for a few years but it was common that Cisco switches were not capable of this.

Gold standard sure, but that doesn't make it the definition of line rate.

Re: Raspberry Pi Pico does line rate 100M Ethernet

#58

Post by baby_souffle »

_flux wrote: post #52
vardump wrote: post #49

Earlier quoted context omitted.

RP2040/2350 are IO monsters. You could for example make a logic analyzer that transfers logic data through ethernet. This "very limited" microcontroller has two cores. Both of them can execute about 25 instructions per byte for generating "application-level traffic". You could definitely saturate a 100 Mbps connection with just one core.

Now that you mention it, I think I would like to see a logic analyzer that does just that. No buffering, just straight up shovel the data to a mac address, or even IP address, and be done with it (maybe lose a few frames here and there). Let the PC worry about what to do with it, like triggers etc. Should be cheap, right? Though 1Gbit version might still be expensive..

How is this different from the cheap salae clones now? Just sub out Ethernet for usb and that’s how they work now: a cheap ic with nothing but a2d and a usb phy samples and sends as fast as it can..

Re: Raspberry Pi Pico does line rate 100M Ethernet

#59

Post by _flux »

baby_souffle wrote: post #58
_flux wrote: post #52

Earlier quoted context omitted.

Now that you mention it, I think I would like to see a logic analyzer that does just that. No buffering, just straight up shovel the data to a mac address, or even IP address, and be done with it (maybe lose a few frames here and there). Let the PC worry about what to do with it, like triggers etc. Should be cheap, right? Though 1Gbit version might still be expensive..

How is this different from the cheap salae clones now? Just sub out Ethernet for usb and that’s how they work now: a cheap ic with nothing but a2d and a usb phy samples and sends as fast as it can..

It would be over the network :), which is—I imagine—tiny bit simpler than over USB.

Re: Raspberry Pi Pico does line rate 100M Ethernet

#60

Post by bangaladore »

MartijnBraam wrote: post #56
bangaladore wrote: post #24

Earlier quoted context omitted.

> Is there enough room to have it control the ethernet port for another weaker or perhaps more powerful microcontroller? Well there is a whole unused core and plenty of built in SRAM. Seems like a good way to have an open-source version of Wiznet chips [1]. It could support full protocol offloading like Wiznet's or a lower-level raw packet sender/receiver like the ENC424J600. [1] https://docs.wiznet.io/Product/iEther…

I just quickly tried to fit the whole rp2040+ethernet phy in the WIZ850io formfactor (mainly because I already used that module in some projects before) and have not yet been able to make it fit without using the more expensive jlcpcb features like burried vias. It would be very cool to have though since the W5500 really needs an update.

A 4-layer in that form factor should be pretty doable with no fancy features like blind vias. The RP2040 and W5500 are the same size, and ethernet PHYs can be found in about 3x3mm or even smaller. There should be about 20x25mm of usable space in that module form factor (even conservatively, like 18x23).

I don't have the time to give it a shot myself, but I could try to help if needed.

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