51–60 of 105 posts
I received mine weeks ago. There are several desktop images but various issues reported from no display output, to only 1080p supported. To this image or that one working. Important note, the later images require an updated to uboot and SPL, either with the bootrom or a serial connection. It's a mess at the moment!
Upstreasming status: https://rvspace.org/en/new-page/JH7110_Upstream_Plan StarFive Tech. have been upstreaming on kernel, OpenSBI and U-Boot from several weeks now. Of course this is still weeks/months away (if not more, for all the features) from landing in stable releases. Even more for distributions to pick those up.
Curious: Is there a "Ferrari" general RISC-V ISA shorthand or CPU implementation with more extensions including Q B V K H & S ?
How well are Linux and the BSDs supported?
- Yocto Linux BSP
- Buildroot Linux BSP
- Embedded Linux from Siemens Embedded
- FreeBSD (coming soon)
https://www.microchip.com/en-us/products/fpgas-and-plds/syst...
Earlier quoted context omitted.
> 1 Processor, 1 Core, 4 Threads Any idea why StarFive went with this choice for an SBC? I remember POWER7 also having 4 SMT, but it felt right for a superscalar multi-core CPU.
The link in the GP comment is wrong - both SoCs have 4 cores, each with a single thread. The reason why this SoC is faster than HiFive Unmatched seems to be down to architectural improvements.
I received mine weeks ago. There are several desktop images but various issues reported from no display output, to only 1080p supported. To this image or that one working. Important note, the later images require an updated to uboot and SPL, either with the bootrom or a serial connection. It's a mess at the moment!
Earlier quoted context omitted.
Still no sign of an actual Technical Reference Manual or any other detailed documentation on the SoC (registers, peripherals, etc). A big pile of Linux patches, while better than nothing, is a poor substitute for actual documentation. SiFive does provide docs for the core complex (processors, cache, irq controller, etc), but that doesn't cover any SoC-specific peripherals.
Agreed. But I feel like that is still a step ahead of RPi where you get random firmware blobs for the GPU without which it won't even boot.
I just find the "all you need is Linux patches" approach annoying. There are BSD variants and little experimental and homebrew OSes out there that would be fun to run on a capable RISC-V SBC and even if you are using Linux it's still nice to have some documentation to refer to beyond whatever the silicon vendor implemented in various driver patches.
Where is the CPU hardware manual that tells me the CPU's memory map and registers? This is why so much hardware ends up in landfills. No thanks to undocumented junk.
https://www.sifive.com/cores/u74-mc
Unfortunately there appears to be no detailed documentation at all (unless you count a pile of Linux and bootloader patches, which I don't) for the peripherals, etc, outside of the core complex on the SoC:
Earlier quoted context omitted.
I haven't looked at the v2 but they seemed to be doing an alright job at getting things upstreamed with the v1. the only thing i remember seeing that wasn't very good in that regard was the neural net stuff that they had and that seemed more from just issues getting the hardware working than any nda or lack of desire to do it. I'd hope that the v2 is similarly worked through even if it needs some non-upstream patches…
It seems like many SoCs (also in ARM space) advertise '2 TOPS' or however many TOPS neural processors integrated in the silicon... but the actual number of SoCs where those coprocessors can be used in Linux seems to be very low.
If your only sell is open hardware, I'm going to wait until the hardware is open to waste my time with it.