HP plans to release first memristor, alternative to flash and SSDs in 18 months • Hacker News Board

Re: HP plans to release first memristor, alternative to flash and SSDs in 18 months

#51

Post by pjscott » Sun, Oct 09, 2011, 7:20 PM UTC

InclinedPlane wrote: post #38

palish wrote: post #35

Earlier quoted context omitted.

I think... Maybe... I'm getting it. Kind of. Probably not. By wiring the CPU directly to the RAM, to use your metaphor, then we can entirely bypass the ASM stage of "a program" (but then what is a program if not a sequence of instructions?) and therefore we may better predict which data our program needs at runtime? Thereby caching that data more effectively than the random access patterns of Von Neumann? Basically,…

Nope, still missing it. When you wire the RAM to the CPU you don't need a cache. Imagine you have a billion or even a trillion registers, or more. That's a non-Von Neumann architecture. You're not shuffling data around on buses, the data is directly connected to the CPU. Look at the example I gave again. Consider a simple addition command. The first CPU instruction says "take the word at this memory address, and move…

Don't need a cache? The larger your memory is, the greater the access latency will be, even if it's directly on the CPU die. That's why L1 and L2 caches tend to be around 32*2 and 256 KB, respectively. Most of the cache access time comes from the wire delays of sending signals around, and the larger the cache is, the longer the wire delays will be.

If you have a bunch of memory directly on the CPU, caching will still give significant speedups.

Re: HP plans to release first memristor, alternative to flash and SSDs in 18 months

#52

Post by viraptor » Sun, Oct 09, 2011, 8:31 PM UTC

zackattack wrote: post #29

viraptor wrote: post #16

Earlier quoted context omitted.

It won't disappear. It could be split, close some sites, change leadership again, etc. but it won't simply cease to exist. The existing infrastructure itself is worth too much.

What would you say are HP's top 5 most valuable pieces of infrastructure?

Just guessing but: lab machines, buildings, purpose-built networks/processing centres, etc. I don't know how the production is organised, but assembly lines may be included.

Re: HP plans to release first memristor, alternative to flash and SSDs in 18 months

#53

Post by georgemcbay » Sun, Oct 09, 2011, 8:40 PM UTC

bluehavana wrote: post #22

plasma wrote: post #14

Watch HP research's Stanley Williams describe the memristor and what they are working towards in more detail on YouTube: http://www.youtube.com/watch?v=bKGhvKyjgLY&sns=em

The no more hard drive and persistent ram thing should be really interesting. Completely change how we do things. Also, application specific processing... writing instruction sets for each application will be really interesting. Cell processing et al will be a thing of the past.

All of those years spent trying to educate my family and non-technical friends on the difference between RAM and HDD and explaining how it is confusing when they tell me they couldn't install a program because their laptop was "out of memory".... wasted!

Re: HP plans to release first memristor, alternative to flash and SSDs in 18 months

#54

Post by rsanchez1 » Mon, Oct 10, 2011, 2:43 AM UTC

A memristor TouchPad would've been really hot.

I wonder how these theoretical projects will survive in an HP that is only concerned with how much profit each project makes to appease shareholders...

Re: HP plans to release first memristor, alternative to flash and SSDs in 18 months

#55

Post by jasonwatkinspdx » Mon, Oct 10, 2011, 4:31 AM UTC

nwatson wrote: post #43

jasonwatkinspdx wrote: post #40

Earlier quoted context omitted.

This is silly. Just because memory is non volatile storage doesn't mean the OS can't do reasonable things like clearing out some state as it goes to sleep.

Ok. So your computer is in lock-screen mode requiring you to enter a password before resuming your interactive session. Someone with physical access to your computer certainly can find a way to divorce the memory from the rest of the system without letting the OS do its thing ... your live program memory is compromised. This memory often will have more sensitive info than your (possibly encrypted) mass storage.

I disagree.

Firstly, the fabrication process everyone is excited about puts the memrister cells directly atop the cmos logic gates as just another layer to the die. No external memory bus to tap into. So you'd need the sort of equipment used to remove layers from dies to expose the cells for reverse engineering, testing, etc. If someone with these resources is after you, you're already fucked regardless of the exact technological vector.

Secondly, a system designer could trivially add some amount of volatile storage for holding security sensitive data. Various schemes of encrypted pages that are decrypted using a key stored in volatile SRM within the CMS could be used. In other words, we could do the same things we currently do with hard drives between the memrister array and SRAM that acts as a decrypted cache.

Thirdly, you're applying an expectation to all memristers that is not applied to existing storage technologies. It might be a fair criticism of a concrete product that operates in an insecure way, but it's absurd to apply this expectation to an entire technology.