Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW • Hacker News Board

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#51

Post by zozbot234 » Fri, Jul 09, 2021, 12:45 AM UTC

KirillPanov wrote: post #46

zozbot234 wrote: post #28

Earlier quoted context omitted.

This impacts the fab itself, but the design rules can still be usable elsewhere since they've been released openly.

Use them where, exactly? Your comment glosses over a ton of critical details. The most important of them being that even on such an old technology generation (180nm-110nm) no two fabs are so compatible that you can send a GDS designed for one of them to the other unless (a) one of them licensed their process from the other, like IBM/GloFo/Samsung back in the 2010s or (b) you planned for this in advance and designed a…

> (a) one of them licensed their process from the other, like IBM/GloFo/Samsung back in the 2010s or (b) you planned for this in advance and designed a custom "least common denominator" process (like MOSIS SCMOS) to target which means making very large performance sacrifices.

The availability of open design rules improves the feasibility of either approach. Any other foundry implementing a 130nm process will be able to refer to the open rules quite directly, with no strings attached - and they will also have very clear incentives to push in that direction. So no, this is not a full fab process, but it's getting remarkably close compared to what we had before.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#52

Post by wallacoloo » Fri, Jul 09, 2021, 1:01 AM UTC

KirillPanov wrote: post #49

wallacoloo wrote: post #29

Earlier quoted context omitted.

I've been keeping an eye out for anything like this. There's Sam Zeloof, doing one-offs in his home lab [1], and there's Libre Silicon [2] putting together their fab too, but the info there's more scarce. Neither one has published an easily-replicable process, meaning I can't really repeat what they've done. IMO what this space needs is an open source build plan/BoM, with a cottage industry of people selling DiY and…

Hey, I admire your spirit and enthusiasm. However, one thing to keep in mind is that below 500nm a lot of the chemicals are extremely toxic and not the kind of thing that garage hackers are qualified to handle in an environmentally safe manner. Arsenic, phosphene gas, hydrogen fluoride, nasty solvents. I build a lot of crazy stuff in my shop, but I don't even trust myself to dispose of these correctly. If makers like…

I’m not hooked on building desktop CPUs at home or anything. It could be 3 um, 1 MHz and I’d be happy. It doesn’t even have to be semiconductors. We had vacuum tubes and core memory before transistors. The modern fab is optimized for density, perf, and power. Prioritize ease of fabrication and maybe you get a process or substrate that looks radically different from today’s commercial fabs.

Or maybe we adopt a 500 nm node and stop there :-)

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#53

Post by phendrenad2 » Fri, Jul 09, 2021, 1:58 AM UTC

I can't wait to see the Vulkan implementation for this. Apparently it should be somewhat hardware-accelerated due to the vector capabilities of the core?

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#54

Post by minetest2048 » Fri, Jul 09, 2021, 3:59 AM UTC

lkcl wrote: post #35

throwawaysea wrote: post #21

Earlier quoted context omitted.

What about the tools and processes to manufacture this? Are those open source or broadly available? For instance, is it possible to have a small scale "community" fab for 1999-era chip technology?

yes, Chips4Makers http://chips4makers.io will help anyone who wants to do a 360nm ASIC, the costs are ridiculously cheap. like... EUR 1750 for 20 MPW samples, something mad, who would have ever thought it. Staf will also "protect" you from the Foundry NDAs. you develop with a "symbolic" version of the Cell Library, he runs the "Real" one and sends it to IMEC on your behalf. here's Staf's "symbolic" Cell Library, it's…

I'm wondering, what's the difference between the 'real' cell library and 'symbolic' cell library?

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#55

Post by kilodeca » Fri, Jul 09, 2021, 4:30 AM UTC

Seirdy wrote: post #27

cdcarter wrote: post #5

Earlier quoted context omitted.

Who is this important for? Is there a lot of software still being developed for POWER? It seems niche to me, but maybe I'm the one in a niche.

Many hyperscalar server setups use POWER8/POWER9 CPUs. 4 logical processes per core (and 8 with the upcoming 15-core POWER10 configurations) are pretty useful when measuring perf-per-watt. The Talos is currently the only fully libre computer available for high-perf computing, and it uses POWER9 CPUs. If you want a fully free CPU, your choices are either very dated CPUs or POWER. Many distros (inc. Debian, and most so…

By Libre computer do you mean the entire system, hardware and firmware?

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#56

Post by Seirdy » Fri, Jul 09, 2021, 6:40 AM UTC

kilodeca wrote: post #55

Seirdy wrote: post #27

Earlier quoted context omitted.

Many hyperscalar server setups use POWER8/POWER9 CPUs. 4 logical processes per core (and 8 with the upcoming 15-core POWER10 configurations) are pretty useful when measuring perf-per-watt. The Talos is currently the only fully libre computer available for high-perf computing, and it uses POWER9 CPUs. If you want a fully free CPU, your choices are either very dated CPUs or POWER. Many distros (inc. Debian, and most so…

By Libre computer do you mean the entire system, hardware and firmware?

Hardware: not necessarily. Firmware: yes.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#57

Post by LargoLasskhyfv » Fri, Jul 09, 2021, 8:39 AM UTC

minetest2048 wrote: post #54

lkcl wrote: post #35

Earlier quoted context omitted.

yes, Chips4Makers http://chips4makers.io will help anyone who wants to do a 360nm ASIC, the costs are ridiculously cheap. like... EUR 1750 for 20 MPW samples, something mad, who would have ever thought it. Staf will also "protect" you from the Foundry NDAs. you develop with a "symbolic" version of the Cell Library, he runs the "Real" one and sends it to IMEC on your behalf. here's Staf's "symbolic" Cell Library, it's…

I'm wondering, what's the difference between the 'real' cell library and 'symbolic' cell library?

Legalese

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#58

Post by lkcl » Fri, Jul 09, 2021, 9:22 AM UTC

Seirdy wrote: post #56

kilodeca wrote: post #55

Earlier quoted context omitted.

By Libre computer do you mean the entire system, hardware and firmware?

Hardware: not necessarily. Firmware: yes.

we'll be going as far as is practical and pragmatic with the actual hardware, and still actually meet user-expectations. firmware, bootloader, OS, drivers, BIOS: definitely.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#59

Post by lkcl » Fri, Jul 09, 2021, 9:31 AM UTC

minetest2048 wrote: post #54

lkcl wrote: post #35

Earlier quoted context omitted.

yes, Chips4Makers http://chips4makers.io will help anyone who wants to do a 360nm ASIC, the costs are ridiculously cheap. like... EUR 1750 for 20 MPW samples, something mad, who would have ever thought it. Staf will also "protect" you from the Foundry NDAs. you develop with a "symbolic" version of the Cell Library, he runs the "Real" one and sends it to IMEC on your behalf. here's Staf's "symbolic" Cell Library, it's…

I'm wondering, what's the difference between the 'real' cell library and 'symbolic' cell library?

they both have the same connections on the outside (they both have the same "netlist") and you can use the exact same SPICE model (a transistor-level simulation) but usually they're entirely empty inside.

so the VLSI tool can still Place-and-Route them, you can still creaate GDS-II Files, but if you send them to the Foundry, the Foundry will look at you like you have two heads or something and won't talk to you again.

that said: some Foundries have their own Symbolic ("ghost") Cell Libraries, which they send you. you run the VLSI tools with those, then when they get the GDS-II files they SUBSTITUTE the REAL cells for the ghost Cells... and then put that into the Fab.

they do this because they're so paranoid they don't even want you to know what's inside their "Symbolic" (ghost) Cells.

Foundry Symbolic Cells are invariably available only under NDA.

sigh.

which begs the question, how the hell is any information is going to leak out from a completely empty Cell, and unfortunately the answer is: quite a lot. number of layers, what the "stack" is of those layers, distance between tracks, width of tracks, and so on, and the PDK also has to include via sizes and so on anyway.

this starts to give you some idea of the levels of insanity we had to workaround, to meet our Audit and Transparency objectives.

bottom line is until we can bust through these final layers of NDAs, customers who really want to verify the complete GDS-II Files are also going to have to sign a Foundry NDA.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#60

Post by swiley » Fri, Jul 09, 2021, 10:34 AM UTC

programmerjake wrote: post #48

swiley wrote: post #8

Earlier quoted context omitted.

IMO: the underlying architecture is mostly relevant to kernel/compiler authors and people doing aggressive optimization. For most application devs it's about as irrelevant as you can get (unless your language has a very hard to port compiler cough rust. ) What's good about this is that the source is available and can be verified to some degree against the hardware (by decapping it.) That puts a log of constraints on…

Rust supports powerpc64le-unknown-linux-gnu, it is in-fact what we used to test a lot of POWER9's instructions to replicate the exact results that POWER9 gives, since the ISA spec doesn't specify the results for a lot of cases. https://git.libre-soc.org/?p=power-instruction-analyzer.git;...

I was talking about new architectures in general, not just powerpc.