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AMD 3rd Gen EPYC Milan Review

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Re: AMD 3rd Gen EPYC Milan Review

#51

Post by dragontamer »

rbanffy wrote: post #48
dragontamer wrote: post #13

Earlier quoted context omitted.

EPYC is a split L3 cache. Any particular core only benefits from 32MBs of L3, the 33rd MB is "on another chip". (EDIT: Zen2 was 16MBs, Zen3 is 32MBs. Fixed numbers for Zen3) As such, AMD can make absolutely huge amounts of L3 cache (well, many parallel L3 clusters), while other CPU designers need to figure out how to combine the L3 so that a single core can benefit it from it all.

What AMD does is not magic and is not beyond what others can do. My question is why they chose to have just 32MB for up to 80 cores when AMD can choose to have 32MB per 8-core chiplet. As a comparison, an IBM z15 mainframe CPU has 10 cores and 256MB per socket.

> As a comparison, an IBM z15 mainframe CPU has 10 cores and 256MB per socket.

Well, that's eDRAM magic, isn't it? Most manufacturers are unable to make eDRAM on a CPU.

> My question is why they chose to have just 32MB for up to 80 cores when AMD can choose to have 32MB per 8-core chiplet.

From my understanding, those ARM chips are largely I/O devices: read from disk -> output to Ethernet.

In contrast, IBM's are known for database backends, which likely benefits from gross amounts of L3 cache. EPYC is general purpose: you might run a database on it, you might run I/O constrained apps on it. So kind of a middle ground.

Re: AMD 3rd Gen EPYC Milan Review

#52

Post by meepmorp »

dragontamer wrote: post #51
rbanffy wrote: post #48

Earlier quoted context omitted.

What AMD does is not magic and is not beyond what others can do. My question is why they chose to have just 32MB for up to 80 cores when AMD can choose to have 32MB per 8-core chiplet. As a comparison, an IBM z15 mainframe CPU has 10 cores and 256MB per socket.

> As a comparison, an IBM z15 mainframe CPU has 10 cores and 256MB per socket. Well, that's eDRAM magic, isn't it? Most manufacturers are unable to make eDRAM on a CPU. > My question is why they chose to have just 32MB for up to 80 cores when AMD can choose to have 32MB per 8-core chiplet. From my understanding, those ARM chips are largely I/O devices: read from disk -> output to Ethernet. In contrast, IBM's are know…

IBM doesn't fab its own chips, right? I thought they used GF.

Re: AMD 3rd Gen EPYC Milan Review

#53

Post by wmf »

meepmorp wrote: post #52
dragontamer wrote: post #51

Earlier quoted context omitted.

> As a comparison, an IBM z15 mainframe CPU has 10 cores and 256MB per socket. Well, that's eDRAM magic, isn't it? Most manufacturers are unable to make eDRAM on a CPU. > My question is why they chose to have just 32MB for up to 80 cores when AMD can choose to have 32MB per 8-core chiplet. From my understanding, those ARM chips are largely I/O devices: read from disk -> output to Ethernet. In contrast, IBM's are know…

IBM doesn't fab its own chips, right? I thought they used GF.

It's basically IBM fabs that were "sold" to GlobalFoundries. AFAIK IBM processors use a customized process that isn't used by any other GF customers.

Re: AMD 3rd Gen EPYC Milan Review

#54

Post by coder543 »

wffurr wrote: post #36
rbanffy wrote: post #8

There must be a typo on the 74F3 price. US$2900 for it is a steal.

RTFA: “ Users will notice that the 16-core processor is more expensive ($3521) than the 24 core processor ($2900) here. This was the same in the previous generation, however in that case the 16-core had the higher TDP. For this launch, both the 16-core F and 24-core F have the same TDP, so the only reason I can think of for AMD to have a higher price on the 16-core processor is that it only has 2 cores per chiplet ac…

I really don't think the article's speculation there is helpful... it's really reaching.

As I said below the article in the comments:

> If I were to speculate, I would strongly guess that the actual reason is licensing. AMD knows that more people are going to want the 16 core CPUs in order to fit into certain brackets of software licensing, so AMD charges more for those to maximize profit and availability of the 16 core parts. For those customers, moving to a 24 core processor would probably mean paying significantly more for whatever software they're licensing.

This is the more compelling reason to me, and it matches with server processors that Intel and AMD have charged more for in the past.

"Even vs odd" affecting the difficulty of the binning process just sounds extremely arbitrary... definitely not likely to affect customer prices, given how many other products are in AMD's stack that don't show this same inverse pricing discrepancy.

Re: AMD 3rd Gen EPYC Milan Review

#56

Post by coder543 »

masklinn wrote: post #19
tecleandor wrote: post #12

Earlier quoted context omitted.

I found it in the original press release (price for !K units, of course) https://ir.amd.com/news-events/press-releases/detail/993/amd...

Still seems like a typo, it doesn't make any sense that the 24 / 48 would be priced between the 8 / 16 and the 16 / 32. Either the prices of the 73 and 74 were swapped or the tag is just plain wrong. "2900" is also very suspiciously round compared to every other price on the press release.

It makes perfect sense if you're an enterprise customer and your software dependencies charge you extremely different priced tiers for different maximum numbers of cores. AMD is selling a license-optimized part at a higher price because there will be plenty of demand for it.

People who don't save a boatload by getting the license-optimized CPU will invariably choose to buy the 24-core one, which helps AMD by making it easier for them to keep up with the demand for the 16-core variant, and the 16-core variant gets an unusually nice profit margin. Win win.

This is not the first time AMD or Intel have offered a weird inverse-pricing jump like this... I highly doubt it is a typo.

My other comment reiterates some of these points a different way: https://news.ycombinator.com/item?id=26469182

Re: AMD 3rd Gen EPYC Milan Review

#57

Post by dragontamer »

rbanffy wrote: post #21
ChuckNorris89 wrote: post #7

Earlier quoted context omitted.

Limitations due to die size and power consumption since Intel Xeon is still on the ye olde 14nm++ process. Also since Xeon dies are monolithic, unlike AMDs chiplet design, means that increasing the size of certain components on the die, like cache for example, increases the risk of defects wich reduces the yields, making them unprofitable.

True, but the ARM ones have just 32MB for up to 80 threads. I wonder if we could get numbers for L3 misses and cycles spent waiting for main memory under realistic workloads.

That information changes with every application. Literally every single program in the world has its own cache characteristics.

I suggest learning to read performance counters, so that you can get information like this yourself! L3 cache is a bit difficult for AMD processors (because many cores share the L3 cache), but L2 cache is pretty easy to work with and profile.

General memory-reads / memory latency is pretty easy to read with various performance counters. Given the amount of latency, you can sorta guess if its in L3 or in DDR4.

Re: AMD 3rd Gen EPYC Milan Review

#58

Post by ChuckMcM »

Nice bump in specs. Perhaps now they will announce the Zen3 Threadripper :-). As others have mentioned the TR can starve itself on memory accesses when doing a lot of cache invalidation (think pointer chasing through large datasets). If the EPYC improvement of having the chiplet CPUs all share L3 cache moved into the TR space (which one might assume it would[1]) then this could be a reason to upgrade.

[1] I may be wrong here but the TR looks to me like an EPYC chip with the mult-CPU stuff all pulled off. It would be interesting to have a decap with the chiplets identified.

Re: AMD 3rd Gen EPYC Milan Review

#59

Post by rodgerd »

coder543 wrote: post #56
masklinn wrote: post #19

Earlier quoted context omitted.

Still seems like a typo, it doesn't make any sense that the 24 / 48 would be priced between the 8 / 16 and the 16 / 32. Either the prices of the 73 and 74 were swapped or the tag is just plain wrong. "2900" is also very suspiciously round compared to every other price on the press release.

It makes perfect sense if you're an enterprise customer and your software dependencies charge you extremely different priced tiers for different maximum numbers of cores. AMD is selling a license-optimized part at a higher price because there will be plenty of demand for it. People who don't save a boatload by getting the license-optimized CPU will invariably choose to buy the 24-core one, which helps AMD by making i…

Yep - in the past I've done "special orders" for not-publicly-advertised CPU configs from our hardware vendor to get low core count, high-clock servers for products like Oracle DB.

Re: AMD 3rd Gen EPYC Milan Review

#60

Post by mrb »

masklinn wrote: post #19
tecleandor wrote: post #12

Earlier quoted context omitted.

I found it in the original press release (price for !K units, of course) https://ir.amd.com/news-events/press-releases/detail/993/amd...

Still seems like a typo, it doesn't make any sense that the 24 / 48 would be priced between the 8 / 16 and the 16 / 32. Either the prices of the 73 and 74 were swapped or the tag is just plain wrong. "2900" is also very suspiciously round compared to every other price on the press release.

It doesn't seem to be a typo. AMD offers many variations of each core configurations, with different base frequencies. It's just that there are simply pricing overlaps between some low-core high-freq version and some higher-core lower-freq versions. For example the 7513 (32 cores) is also cheaper than the 73F3 (16 cores).

  75F3 32-core 2.95GHz $4,860
  7543 32-core 2.80GHz $3,761
  7513 32-core 2.60GHz $2,840
  
  74F3 24-core 3.20GHz $2,900
  7443 24-core 2.85GHz $2,010
  7413 24-core 2.65FHz $1,825
  
  73F3 16-core 3.50GHz $3,521
  7343 16-core 3.20GHz $1,565
  7313 16-core 3.00GHz $1,083
Source: https://ir.amd.com/news-events/press-releases/detail/993/amd...
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