Good reference!
FPGA Design for Software Engineers
51–60 of 84 posts
Re: FPGA Design for Software Engineers
#52This is a pretty nice tutorial! My courses in FPGA design in school taught me a ton about 1) concurrency and 2) good state machine design. In modern backend web development these topics receive so little attention (from interviewing all the way to writing technical specs, I've rarely encountered these topics brought up explicitly) but are important. I was a bit hesitant for this guide to suggest using C++ since I ten…
I disagree about for loops, you actually end up using these quite a lot in vhdl/verilog (with understanding about what logic you are going to end up with), if you want to do the same operation on multiple things:
input [NUM_OF_MULTIPLIERS*32-1:0] a_in,
input [NUM_OF_MULTIPLIERS*32-1:0] b_in,
output [NUM_OF_MULTIPLIERS*64-1:0] mult_out
reg [31:0] tmp_a, tmp_b;
reg [63:0] tmp_mult;
always @(*) begin
mult_out = {(NUM_OF_MULTIPLIERS*64){1'b0}};
for (i=0; i>(i*32);
tmp_b = b_in>>(i*32);
tmp_mult = tmp_a*tmp_b;
mult_out |= tmp_multRe: FPGA Design for Software Engineers
#53little nitpick:
it's "combinational circuits", not "combinatorial" (that's whole another part of math)
Re: FPGA Design for Software Engineers
#54Great article, I wish the discussions around clocks had gone a bit more into how the tradeoff of pipelining vs longest operation ends up impacting designs. That and SRAM vs DRAM access latencies were the things that really connected the dots from how performance optimization on the software side of things is rooted in physical hardware limitations.
Might you or anyone else have some links or references you could share on these two topics? Was there a specific book that helped connect the dots that you could recommend?
Here's a greatly simplified example. Let's say you're trying to calculate y = mx + b in your FPGA. You want this operation to run at 100 MHz. Great, you write the code, synthesize and implement. Uh oh, the tools report that your design has failed timing analysis. What now?
Looking at the output of the tools, they'll say something like "x to y setup time: -2 ns slack". That means your desired operation can't meet the 10 ns clock period; it actually takes 12 ns for all the logic to ripple through. So now what?
You can break up the operation into two steps. Let's say the multiplication takes 8 ns, and the addition takes 4 ns. In timestep 1 you do z = mx, and pipeline c = b. Then in timestep 2 you do y = z + c. This way your operation takes two clock cycles = 20 ns total in terms of latency, but you can maintain a rate of 100 MHz.
Alternatively, you could choose a slower clock rate, say 75 MHz, and have a clock period of 13.333 ns. Then you would be able to meet the logic delay requirements in one cycle.
Again this is greatly simplified but it's similar to what one ends up doing in real FPGA designs. At the beginning you're usually trying to achieve maximum performance. Then later on you add more features to the FPGA, only to find that in doing so, you've caused an existing portion of the design to fail timing, so you need to twiddle things around.
Re: FPGA Design for Software Engineers
#55Re: FPGA Design for Software Engineers
#56little nitpick: it's "combinational circuits", not "combinatorial" (that's whole another part of math)
Do you have a reference for that? I'm genuinely curious since both terms are used in literature.
Re: FPGA Design for Software Engineers
#57That's a good intro. What I always have to remind software guys who switch to FPGA design is remember each line you write is eventually going to end up in hardware.
That means when you write something you should have some understanding of the underlying hardware inferred. So is this going to give me some combinatorial logic, a register or a RAM? It's very easy to keep the software mindset of if it compiles then it's good.
Re: FPGA Design for Software Engineers
#58I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications. What I am missing are 2 topics: timing analysis and debugging. Static timing analysis and proper timing constrains are crucial for functional design. No tool can differentiate without constrains a slow signal signal toggling LED every 10 seconds from DDR3 533 MHz differential c…
> I am curious, why System Verilog isn’t mentioned in this article. It is much much better than Verilog and is used in industrial applications.
Probably because it has very limited support in open source tooling, same as VHDL.
Re: FPGA Design for Software Engineers
#59little nitpick: it's "combinational circuits", not "combinatorial" (that's whole another part of math)
Do you have a reference for that? I'm genuinely curious since both terms are used in literature.
"combinatorial" was used predominantly in 1970s books for whatever reason.
In most of contemporary books and university courses "combinational" is used and with a note that you should not confuse it with "combinatorics" and "combinatory logic"
Re: FPGA Design for Software Engineers
#60This is a pretty nice tutorial! My courses in FPGA design in school taught me a ton about 1) concurrency and 2) good state machine design. In modern backend web development these topics receive so little attention (from interviewing all the way to writing technical specs, I've rarely encountered these topics brought up explicitly) but are important. I was a bit hesitant for this guide to suggest using C++ since I ten…
I disagree about for loops, you actually end up using these quite a lot in vhdl/verilog (with understanding about what logic you are going to end up with), if you want to do the same operation on multiple things: input [NUM_OF_MULTIPLIERS*32-1:0] a_in, input [NUM_OF_MULTIPLIERS*32-1:0] b_in, output [NUM_OF_MULTIPLIERS*64-1:0] mult_out reg [31:0] tmp_a, tmp_b; reg [63:0] tmp_mult; always @(*) begin mult_out = {(NUM_OF…
The key is that for loops are essentially pre-processor macros (like C) so they must have a fixed number of iterations known at compile time. So yes, you have a for loop, but it's very different to what you expect from a for loop in software.