Earlier quoted context omitted.
I don't understand why these two performance measures would not track perfectly, since the CPUs should be running a constant number of cycles/second. x86 isn't RISC and not all operations take the same number of cycles. Also, the code might have different levels of possible parallelism and might impact the pipeline differently. Comp Sci education for the low level basics is often completely neglected nowadays. This s…
> x86 isn't RISC and not all operations take the same number of cycles. Yes but it doesn't say instructions per hash, it says cycles per hash. Unless some kind of frequency scaling is going on, the number of cycles per second should be very consistent. If bytes/hash is held constant and cycles/second is constant, then MiB/second and cycles/hash should be exact inverses. I don't understand why this is not the case in…
Those would be the useful numbers.