51–60 of 81 posts
From The Next Platform ( https://www.nextplatform.com/2018/05/24/a-peek-inside-that-i... ): The initial workload that Intel is targeting is putting Open Virtual Switch, the open source virtual switch, on the FPGA, offloading some switching functions in a network from the CPU where such virtual switch software might reside either inside a server virtualization hypervisor or outside of it but alongside virtual machines…
Earlier quoted context omitted.
That seems like a weak benefit. I don't think the fpga part will be cheap. In fact it will probably be significantly more expensive than the CPU. So then why not buy a chip with twice the cores if running twice the VMs is what you want to do with it? Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores.
>Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores. Indeed. What benefits the most from being turned into FPGA circuit are stateless or minimally stateful circuits like media decoders/encoders. Complex stuff like fancy routers, classifiers, internet protocol inspection/handling will not gain a hundredfold speedup unlike th…
Can you share how this FPGA and RDMA combination works architecturally? What's the software stack composed of? Might you have any links or other resources you could share?
This is great! I think that some time in the future, FPGA will be a vital part for data processing. In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body). What I am worried about is the infrastructure that is needed to make this happen: Is there even support for this in our compilers? What would support look like?
> think the hot innermost loop body In many applications data access is the bottleneck, and an FPGA coprocessor will not give any improvements in that area. Using an FPGA to do arithmetic computations (e.g. as in audio/video coding) could provide a benefit, but I fail to see how this improves things much over having an extra CPU core. The only thing an FPGA does is replace registers by wires, basically, and there's n…
This is great! I think that some time in the future, FPGA will be a vital part for data processing. In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body). What I am worried about is the infrastructure that is needed to make this happen: Is there even support for this in our compilers? What would support look like?
Back in the mid-to-late nineties, Federico Faggin, designer of Intel's seminal 4004 (and ancestor of the whole x 86 lineage) co-founded a company called Starbridge Systems that aimed to construct and sell what they termed hypercomputers whose architecture was rapidly-reconfiguring FPGAs that an enabled a compile-to-hardware model. Here's one of the few references to that project that I can now find online, a WIRED er…
This is great! I think that some time in the future, FPGA will be a vital part for data processing. In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body). What I am worried about is the infrastructure that is needed to make this happen: Is there even support for this in our compilers? What would support look like?
Earlier quoted context omitted.
Phi is dead. The next NERSC computer is GPUs. Not sure what Argonne is doing but there’s no reason to think it won’t be GPUs. The only reason Phi/KNL made sense was because it seemed like a conservative choice when GPUs were more exotic, which may have been okay if Intel didn’t have the crazy yield problems they had. FPGAs don’t make sense because the conservative choice at this point is GPU. I don’t think any of the…
> The next NERSC computer is GPUs. Got a source on this? I've not seen an official mention of what sort of architecture NERSC-9 will be. > Not sure what Argonne is doing but there’s no reason to think it won’t be GPUs. It will be a future Intel processor [1]. [1] https://www.hpcwire.com/2017/09/27/us-coalesces-plans-first-...
From The Next Platform ( https://www.nextplatform.com/2018/05/24/a-peek-inside-that-i... ): The initial workload that Intel is targeting is putting Open Virtual Switch, the open source virtual switch, on the FPGA, offloading some switching functions in a network from the CPU where such virtual switch software might reside either inside a server virtualization hypervisor or outside of it but alongside virtual machines…
That seems like a weak benefit. I don't think the fpga part will be cheap. In fact it will probably be significantly more expensive than the CPU. So then why not buy a chip with twice the cores if running twice the VMs is what you want to do with it? Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores.
This is great! I think that some time in the future, FPGA will be a vital part for data processing. In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body). What I am worried about is the infrastructure that is needed to make this happen: Is there even support for this in our compilers? What would support look like?
> In theory, an application with a computation-heavy task could program the FPGA to provide part of that task in hardware (think the hot innermost loop body). This is absurdly far away; it reminds me of the decades of assumption that 4GLs are going to obsolete programmers or the decades of trying to cross-compile C to FPGAs, badly. It doesn't help that there's a huge infrastructure barrier caused by closed tools. Ima…
I agree with you about the problems of closed-source - but I feel like the end of Moore's law will encourage creative solutions to performance problems - which FPGAs would at least make technically possible. And, even if it's like the old days when people bought compilers and access to source, people will still do it - since it'll be the best way to get an edge on the competition.
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Pretty sure that Phi as you know it is largely being left. Argonne's Aurora exascale machine was suppose to be Xeon Phi, but it has been postponed till 2021 and will likely use some other tech. Also look at the top 500 list from late 2017. Trinity the NNSA computer at #7 is Phi based but only gets about 50% of theoretical peak.
My personal tinfoil hat take is that Xeon Phi was made to make China waste top dollar on their supercomputers going with a less useful accelerator made by a US company.
From The Next Platform ( https://www.nextplatform.com/2018/05/24/a-peek-inside-that-i... ): The initial workload that Intel is targeting is putting Open Virtual Switch, the open source virtual switch, on the FPGA, offloading some switching functions in a network from the CPU where such virtual switch software might reside either inside a server virtualization hypervisor or outside of it but alongside virtual machines…
That seems like a weak benefit. I don't think the fpga part will be cheap. In fact it will probably be significantly more expensive than the CPU. So then why not buy a chip with twice the cores if running twice the VMs is what you want to do with it? Also you can buy an AMD EPYC chip with twice the cores for about the same price you'd pay only for the CPU part of this chip/half the intel cores.
Pretty narrow still, but the market segment is possibly real.