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LowRISC: Open-source RISC-V SoC

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Re: LowRISC: Open-source RISC-V SoC

#41
post #28

Earlier quoted context omitted.

That raises an interesting point -- the original MIPS ISA hasn't been patent encumbered in quite a while (and even then, only two non-essential instructions were patent protected). Why should a person is this unknown ISA instead of MIPS?

I think it may be to avoid any political/legal issues - despite the patents having expired, MIPS still sells ISA licenses. On the other hand, RISC-V basically is most of MIPS (but most RISC ISAs are very similar anyway). They also avoided the patented instruction issue completely by removing all alignment restrictions from the regular load/store; probably a good idea, with memory bandwidths being the bottleneck now a…

The specification (http://riscv.org/riscv-spec-v2.0.pdf) clearly states the reasons. It has nothing to do with political/legal issues. There are very good technical reasons for designing a new ISA.

That RISC-V resembles MIPS is a testament to what was good about the MIPS design, however if you look closely you will find the many ways in which RISC-V is different.

Truly, the specification is highly readable and the footnotes enjoyable. Having implemented multiple MIPS cores and so far one RISC-V core, I'm deeply impressed with the care that went into the design.

Re: LowRISC: Open-source RISC-V SoC

#42
post #39
post #10

That hardware implementation of RISC-V listed on their website is written in Scala (using Chisel). That's very cool. I want to see synthesis results.

Hi, are you talking about the Sodor cores? I wrote those and wouldn't mind answering any questions about RISC-V or Chisel. Regarding Sodor, they're designed to be instructional (we use them on our undergrads at Berkeley) and open for anybody with a C++ compiler so they can learn about Chisel and RISC-V. I pushed them through synthesis once just for kicks, but I didn't work on making them FPGA-ready. Chisel will give…

Hey, I've been interested in RISC-V and Chisel, and am a bay area local (Live in Oakland)... what is the best way to get in contact with you and others at UCB?

Re: LowRISC: Open-source RISC-V SoC

#43
post #39

Earlier quoted context omitted.

Hi, are you talking about the Sodor cores? I wrote those and wouldn't mind answering any questions about RISC-V or Chisel. Regarding Sodor, they're designed to be instructional (we use them on our undergrads at Berkeley) and open for anybody with a C++ compiler so they can learn about Chisel and RISC-V. I pushed them through synthesis once just for kicks, but I didn't work on making them FPGA-ready. Chisel will give…

Hey, I've been interested in RISC-V and Chisel, and am a bay area local (Live in Oakland)... what is the best way to get in contact with you and others at UCB?

Hmmm, I actually have no idea!

Chisel has a google group that you can post any comments or questions you have (chisel.eecs.berkeley.edu). If you wait a week, we should have something similar up at (riscv.org) too.

Chisel has an occasional "boot-camp" where you can come and learn how to use it, and RISC-V will have something similar too I believe in January.

Re: LowRISC: Open-source RISC-V SoC

#44
post #39
post #10

That hardware implementation of RISC-V listed on their website is written in Scala (using Chisel). That's very cool. I want to see synthesis results.

Hi, are you talking about the Sodor cores? I wrote those and wouldn't mind answering any questions about RISC-V or Chisel. Regarding Sodor, they're designed to be instructional (we use them on our undergrads at Berkeley) and open for anybody with a C++ compiler so they can learn about Chisel and RISC-V. I pushed them through synthesis once just for kicks, but I didn't work on making them FPGA-ready. Chisel will give…

Yes, that's what I was talking about. Dave Patterson was giving a talk in Portland about three years ago on heterogeneous computing, and he mentioned Chisel. And now it seems to be relatively mature. I am happy to see innovation in both the HDL and uArch space.
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