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80386 microcode disassembled

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Re: 80386 microcode disassembled

#41

Post by anthk »

drivers99 wrote: post #15
mettamage wrote: post #2

For me, this is peak Hacker News. I am happy I took the hard courses at uni to understand a post like this. I’m also happy that HN was there to stimulate this thinking at the time (2015). Even if I now don’t really do anything with my humble knowledge of low level programming, every time it feels consciousnesses enriching. And it’s an awesome feeling. For people that don’t have access to a uni, I recommend nand2tetri…

I did nand2tetris a couple times, but it emphasizes simplicity in every level of abstraction. That in itself is an amazing lesson and has been an inspiration, but that also means it skips things like microcode. In college (in the 1990s) I took a EE class as part of my CS degree that went through how an 8086-like[0] CPU is made, a lot like nand2tetris but without necessarily making each part an assignment. It did cove…

You might like this, a CPU made by TTL's running Minix 2.

https://www.homebrewcpu.com/

I might upload Tristam Island (Z-Machine v3 game, like Zork and infocom games they already have the interpreter) among the feelies in ASCII format. Yes, dfrotz runs snappier than the vi clone they have. And more stable than their ed implementation.

Re: 80386 microcode disassembled

#42

Post by phire »

Dwedit wrote: post #26

Meanwhile the original ARM didn't use any microcode at all.

I wouldn’t say it didn’t have any microcode. It actually had a small PLA for sequencing the multi-cycle instructions. [0]

I don’t think anyone would actually label it as microcode (not when the entire point of RISC was to avoid microcode) they would call it a sequencer or finite state machine; But really it’s the same thing. It’s certainly much simpler than the full microcode of any contemporary CISC, and the bulk of instructions execute in a single cycle without using it.

If you want a design with zero microcode, you really need to look at MIPS, or the original Berkeley RISC. Those ISAs go out of their way to avoid multicycle instructions. Not entirely successfully, but they don't use PLAs [1] to implement any state machines for the few remaining instructions like multiply and divide.

[0] http://daveshacks.blogspot.com/2016/01/inside-armv1-instruct...

[1] At least on the few MIPS designs I've looked at. And I'm not sure if they deliberately avoided PLAs for doctrine reasons, or it was just more efficient to do so.

Re: 80386 microcode disassembled

#44

Post by Dwedit »

themafia wrote: post #35
Dwedit wrote: post #26

Meanwhile the original ARM didn't use any microcode at all.

Yet their purity brought them no commercial benefit.

ARM got all the commercial benefit once they switched from making chips to providing full designs ready to integrate into other chips.

Re: 80386 microcode disassembled

#47

Post by themafia »

Dwedit wrote: post #44
themafia wrote: post #35

Earlier quoted context omitted.

Yet their purity brought them no commercial benefit.

ARM got all the commercial benefit once they switched from making chips to providing full designs ready to integrate into other chips.

> to providing full designs ready to integrate

Yes, once the market came into existence, ARM was well situated to take advantage of it.

> all the commercial benefit

"All" is a tricky term to use here. They got some. An appreciable amount even. Their business model leaves quite a bit on the floor compared to desktop chips.

Re: 80386 microcode disassembled

#49

Post by rep_lodsb »

userbinator wrote: post #46

I agree with the first comment there, that it's important to know which revision of the 386 this came from, since the 386 did receive many small changes over its 22-year production run.

Well, one indication is the value loaded into EDX on reset:

    9B5 BIST1  -> TMPD    0x0303         PASS2
    9B6 SIGMA  -> EDX
    9B7 BIST2  -> TMPE    TMPD           XOR
    9B8 SIGMA             0x3ddc0c2c     XOR
    9B9 SIGMA  -> EAX     BOOTUP_JUMP    JFPUOK
0x303 = family 3, model 0, stepping id 3.

Re: 80386 microcode disassembled

#50

Post by userbinator »

rep_lodsb wrote: post #49
userbinator wrote: post #46

I agree with the first comment there, that it's important to know which revision of the 386 this came from, since the 386 did receive many small changes over its 22-year production run.

Well, one indication is the value loaded into EDX on reset: 9B5 BIST1 -> TMPD 0x0303 PASS2 9B6 SIGMA -> EDX 9B7 BIST2 -> TMPE TMPD XOR 9B8 SIGMA 0x3ddc0c2c XOR 9B9 SIGMA -> EAX BOOTUP_JUMP JFPUOK 0x303 = family 3, model 0, stepping id 3.

That's either a B0 or B1 according to https://www.pcjs.org/documents/manuals/intel/80386/ , or an A3 according to https://www.geoffchappell.com/studies/windows/km/cpu/precpui... , all of which are very buggy.
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