41–50 of 50 posts
I’m a fan of this, although I’m concerned about the security/trust model: using a third-party CI orchestrator on top of GHA means trusting them with all of your secrets, potentially sensitive logs, etc. Those concerns are somewhat lessened in the context of public repos, but even public repos contain nontrivial workflows that use configured secrets.
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Oftentimes slow is fine, when the work is parallel and the hardware is cheap
RISC-V microcontrollers are inexpensive but “application” processors will be expensive until volumes increase. Performance will get “good enough” over the next 2 years. Prices will drop after that.
“Good enough” here was meant to mean good enough to sell more, and therefore to drop prices.
That is already happening. It just needs to happen more. And I think it will. If you don’t find the RISC-V boards of 24 months from now “good enough”, that is ok with me. I just want them to get cheaper.
The other thing that is happening on that front is that microcontrollers are getting more powerful and staying inexpensive. You can get RISC-V microcontrollers today with similar performance to the original Raspberry Pi and with things like WiFi, Bluetooth, and USB. They are crazy cheap and there are many projects for which they are now “good enough”. And, of course, they keep getting better.
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That has been the case so far but is changing this year. The SpacemiT K3 is faster than QEMU. Much faster chips are expected to release over the next few months. I mean things like the Milk-V Pioneer were already faster but expensive. One thing that has been frustrating about RISC-V is that many companies close to releasing decent chips have been bought and then those chips never appear (Ventana, Rivos, etc). That an…
One thing I observed is that RVV code is usually slower in QEMU
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which, sadly, isnt the case right now
It is the case for embedded microcontrollers. An ESP32-C series is about as cheap as you can get a WiFi controller, and it includes one or more RISC-V cores that can run custom software. The Raspberry Pi Pico and Milk-V Duo are both a few dollars and include both ARM and RISC-V view. with all but the cheapest Duo able to run Linux.
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The RISC-V ISA can be fast. Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years. The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation). This should give you an idea about how fast RISC-V is improving.
I'd be pretty surprised if Ascalon actually hits Zen 5 perf (I'm gessing more like Zen2/3 for most real world workloads). CPU design is really hard, and no one makes a perfect CPU in their first real generation with customers. Tenstorrent has a good team, but even the "simple" things like compilers won't be ready to give them peak performance for a few years.
I can't see any reason why the father of Zen and the designer of the M1 can't make a core for the simpler RISC-V ISA with basically the same (or better) µarch than the M1.
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That the "good enough" SoCs will be arriving "over the next 2 years" is what the RISC-V advocates have told us for quite a few years now.
Well, part of “good enough” is features. The RVA23 profile was ratified a few months ago and the first chips are appearing now. That brings RISC-V to feature parity with X86-64 and ARM, including things like vector instructions and virtualization. QUbuntu 26.04 is compiled to require RVA23. So, the RISC-V advocates got that part right. Of course, the other side of “good enough” is performance. The SpacemiT K3 has the…
If you're like me, you're suffering the typical time dilation that comes with getting old.
For everybody else, this was 18 months ago.