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Two Weeks Until Tapeout

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Re: Two Weeks Until Tapeout

#41

Post by lizknope »

random_duck wrote: post #40
lizknope wrote: post #38

Earlier quoted context omitted.

The other alternative is that you sprinkle spare gates around the chip. If the chip is 10mm x 10mm then every 100 microns you put a group of cells that just have their inputs tied to 0 and the outputs go nowhere. You put in a good mix of flip flops, and combinational logic cells. Then when you need to do a metal ECO the RTL team says "We need 2 AND gates, 1 OR gate, 1 mux, and they are connected to these 5 cells." So…

So you want to sprinkle the faster cell groups around, but the ecofiller gates are more flexible since they are everywhere by default ? > Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers. Oh, I had no idea that was a thing.

I've been doing this for 30 years.

Blocks are never 100% full. If it was then you would never be able to route the design. High utilization may be 70% but if a block has tons of IO then I've worked on blocks that are only 25% utilized. For various manufacturing and yield purposes the empty spaces need filler cells.

Sometimes we put in decoupling cap cells. But the ecofiller cells go in everywhere else.

About 25 years ago we were using spare gates that we had preplaced on the die.

About 5 years ago we started using spare gates preplaced and ALSO the ecofiller cells. The reason I was told was to save money because the ecofiller cells require some other mask layer to change. I think that was in the $500K range but it's still money.

In general I hate doing ECO's with the preplaced spare gates as it is manual and time consuming to find the best cells to use.

Re: Two Weeks Until Tapeout

#42

Post by caisley »

random_duck wrote: post #36
caisley wrote: post #22

Earlier quoted context omitted.

I work in custom CMOS image sensor design, targeting scientific imaging applications like electron microscopes, X-ray microscopy, and detectors for high-energy physics. Our designs aren't that cost sensitive from a unit cost perspective, because we are at most probably making several thousand of the chips. So the cost per chip can effectively range from 10-100$ at this scale, after yield losses. But the fixed costs o…

Oh thanks, this is really interesting. Is there a limit to how far you can scale down your node to build the full frame image sensor: is 180nm the largest feasible node?

Modern commercial image sensors are made in process nodes down to 28nm [0], and for visible light have pixels measuring 0.7-1.5 μm. At [0] there a diagram which gives a feel for what technology nodes are available and used for different applications. For example, RF ICs and power management ICs also typically use larger process nodes, and not just for reasons of cost. In fact a larger node, doesn't necessarily even mean older. For example, many technologies allowing better power handling capabilities in integrated circuits have come exclusively to larger nodes.

Regarding node sizes for image sensors, TSMC built a 28nm fab recently for Sony exclusively to make their latest sensors. There was actually a HN post about that a couple years ago [1]. Also, it's important to note that in many applications, the image sensor layer is now actually stacked, with a layer of DRAM (in 45 nm, for example) between, and a ISP (image signal processor) chip on the bottom made in a smaller digital process. You can see an image of that stack up here [2].

[0] https://image-sensors-world.blogspot.com/2020/08/tsmc-report... [1] https://news.ycombinator.com/item?id=24321804 [2] https://fuse.wikichip.org/news/763/iedm-2017-sonys-3-layer-s...

Re: Two Weeks Until Tapeout

#43

Post by caisley »

lizknope wrote: post #33
caisley wrote: post #29

Earlier quoted context omitted.

Can I ask how often you guys end up doing gate-level netlist ECOs, instead of re-running synthesis when you're close to a deadline? Also, post-fabrication, if a mistake is found, have you been able to fix it just with a new M1 or M2 mask, instead of paying for a full new mask set?

If the change is under 1000 logic cells and no new flip flops then we do a it as an ECO. If there are tons of new flip flops we resynthesize and start over. Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of…

Wow, awesome thanks for the details! I have once or twice on projects added extra gates as fillers in some 28nm mixed-signal designs for metal layer re-work, but I had no idea that in larger digital teams there was also the practice of adding these types of individual transistor arrays. Super clever!

Re: Two Weeks Until Tapeout

#44

Post by random_duck »

caisley wrote: post #42
random_duck wrote: post #36

Earlier quoted context omitted.

Oh thanks, this is really interesting. Is there a limit to how far you can scale down your node to build the full frame image sensor: is 180nm the largest feasible node?

Modern commercial image sensors are made in process nodes down to 28nm [0], and for visible light have pixels measuring 0.7-1.5 μm. At [0] there a diagram which gives a feel for what technology nodes are available and used for different applications. For example, RF ICs and power management ICs also typically use larger process nodes, and not just for reasons of cost. In fact a larger node, doesn't necessarily even m…

This is great: thanks for all this.

Re: Two Weeks Until Tapeout

#45

Post by choilive »

pjc50 wrote: post #25
CrispinS wrote: post #3

The thing I love about blog posts like these is how it reminds me that the tech world is a vast ocean that encompasses so many disciplines; it's not all full stack web development. Related: I did not understand 95% of what she wrote.

On some of my cover letters I wrote "full stack from the transistors upwards", because at one point or another I have shipped code in: - IC design software (at a startup bought by Cadence) - an IC (contract out of Dallas semi) - FPGA HFT acceleration - fixing some OS drivers for Windows CE - finding a compiler bug - various bits of embedded firmware in C and assembly for various platforms - debugging with a scope - d…

> Somehow I've never written a react app.

Count your blessings.

Re: Two Weeks Until Tapeout

#46

Post by SilverElfin »

As someone who isn’t familiar with the deep details of the hardware side of the AI industry, I’m curious if these chips are “easy” to write AI software for, or if there is a big barrier. How significant is Nvidia’s moat on the software layer, which I often see talked about in articles, when people seem to be willing to adopt AI accelerators. And if AI accelerators can be adopted, why aren’t other competitors to Nvidia (AMD, Intel, etc) able to break in?

Re: Two Weeks Until Tapeout

#47

Post by random_duck »

choilive wrote: post #45
pjc50 wrote: post #25

Earlier quoted context omitted.

On some of my cover letters I wrote "full stack from the transistors upwards", because at one point or another I have shipped code in: - IC design software (at a startup bought by Cadence) - an IC (contract out of Dallas semi) - FPGA HFT acceleration - fixing some OS drivers for Windows CE - finding a compiler bug - various bits of embedded firmware in C and assembly for various platforms - debugging with a scope - d…

> Somehow I've never written a react app. Count your blessings.

lol

Re: Two Weeks Until Tapeout

#48

Post by lesser-shadow »

As a person that is using Librelane daily in their workflow, why did they skip Gate-level simulation? Iverilog won't ensure the circuit works after tapeout, CVC most likely will. SDF-annotated simulation actually shows data hazards, as well as transistor timings.

https://librelane.readthedocs.io/en/latest/usage/timing_clos...

Re: Two Weeks Until Tapeout

#49

Post by lesser-shadow »

random_duck wrote: post #15
mcny wrote: post #11

Earlier quoted context omitted.

I didn't even know that 180nm was still a thing but clearly it is because apparently the cost difference is like USD 100M for 180nm vs USD 10B or more for the latest tech? Is it true that we will likely have these 180nm chips for things like light bulbs for the foreseeable future?

More thank light bulbs. As you have correctly pointed it out, its a matter of economics: 180nm is CHEAP! So a lot more things become economically viable, think of all the weird specialized ASICs that used to be to expensive to build.

Not only that, but 180nm/130nm is the only option that is OpenSourced, as of now. Transistor Libraries for ICs (or, PDKs) have long been proprietary. I'm only aware of IHP and Sky130, which are actually banking on Fossi or Libre Silicon design.

Re: Two Weeks Until Tapeout

#50

Post by random_duck »

lesser-shadow wrote: post #48

As a person that is using Librelane daily in their workflow, why did they skip Gate-level simulation? Iverilog won't ensure the circuit works after tapeout, CVC most likely will. SDF-annotated simulation actually shows data hazards, as well as transistor timings. https://librelane.readthedocs.io/en/latest/usage/timing_clos...

> Once again, I used Cocotb as the abstracting layer allowing me to interface with multiple different simulators. Namely, icarus verilog for my standard verification and CVC for the post implementation timing annotated netlist.
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