It seems to me that there are exactly 3 buyers for FPGAs: Government contractors (who spend millions all at once), retro gamers (small market), and electronics hobbyists (another small market). It's no wonder every company has orientated itself towards the first one. I look to China to accidentally make chips that are an order of magnitude better "just because they can".
FPGAs Need a New Future
41–50 of 170 posts
Re: FPGAs Need a New Future
#42FPGAs need their "Arduino moment". There have been so, so, so many projects where I've wanted just a little bit of moderately-complicated glue logic. Something pretty easy to dash off in VHDL or whatever. But the damn things require so much support infrastructure: they're complicated to put down on boards, they're complicated to load bitstreams in to, they're complicated to build those bitstreams for, and they're com…
> they're complicated to put down on boards https://gowinsemi.com/en/product/detail/46/ - Requires just 1V2 + 3V3 - Available in QFN - Bitstream is saved in internal flash or programmed to SRAM via a basic JTAG sequence https://www.efinixinc.com/products-trion.html
The Altera Max 10 devices are also relatively simple to support (flash on the chip, few power rails, etc.)
Re: FPGAs Need a New Future
#43Earlier quoted context omitted.
VHDL is ok, Verilog is a sin. The issue isn't the languages, it's the horrible tooling around them. I'm not going to install a multi GB proprietary IDE that needs a GUI for everything and doesn't operate with any of my existing tools. An IDE that costs money, even though I already bought the hardware. Or requires an NDA. F** that. I want to be able to do `cargo add risc-v` if I need a small cpu IP, and not sacrifice…
Well really, the language _is_ the difficulty of much of hardware design, both Verilog and VHDL are languages that were designed for simulation of hardware, and not synthesis of hardware. Both languages have of similar-but-not-quite ways of writing things, like blocking/nonblocking assigns causing incorrect behavior that's incredibly difficult to spot on the waveform, not being exhaustive in assigns in always blocks…
VHDL was designed for specification. Verilog is the one with the warts from its simulator heritage.
Re: FPGAs Need a New Future
#44Earlier quoted context omitted.
You can pretty much do everything in Vivado from the command line as long as you know Tcl... Also, modern Verilog (AKA Systemverilog) fixes a bunch of the issues you might have had. There isn't much advantage to VHDL these days unless perhaps you are in Europe or work in certain US defense companies.
The main advantage to VHDL is the style of thinking it enforces. If you write your Verilog or SystemVerilog like it's VHDL, everything works great. If you write your VHDL like it's Verilog, you'll get piles of synthesis errors... and many of them will be real problems. So if you learn VHDL first, you'll be on a solid footing.
There is a trend among programmers to assume that everything supported by the syntax can be done. This is not even true in C++, but it's something people think. If you are writing synthesizable SystemVerilog, only a small subset of the language used in a particular set of ways works. You have to resist the urge to get too clever (in some ways, but in other ways you can get extremely clever with it).
Re: FPGAs Need a New Future
#45On the software front as mentioned VHDL and Verilog are showing their age with their design as well as ther tooling ecosystem.Attempts such as CHISEL[1] (written in Scala)also havent gotten much traction - seeing also the language choice - would have btter have been in something more accesible like kotlin/ocaml.
Secondly the integration with consumer devices and OS is almost non-ecistant - it should really be simpler to interact with ala GPU/Network chip and have more mainboards with lowcost integrated FPGAs even if they are only a couple of hundred of logic cells.
[1]https://github.com/chipsalliance/chisel/blob/main/README.md
Re: FPGAs Need a New Future
#46Earlier quoted context omitted.
VHDL is ok, Verilog is a sin. The issue isn't the languages, it's the horrible tooling around them. I'm not going to install a multi GB proprietary IDE that needs a GUI for everything and doesn't operate with any of my existing tools. An IDE that costs money, even though I already bought the hardware. Or requires an NDA. F** that. I want to be able to do `cargo add risc-v` if I need a small cpu IP, and not sacrifice…
Or you could do the right thing, ignore the GUI for 99% of what you’re doing, and treat the FPGA tools as command line tools that are invoked by running “make”…
This is how most FPGA users interact with vivado/quartus these days.
Re: FPGAs Need a New Future
#47Earlier quoted context omitted.
The strong point of FPGAs is their versatility. If you wanted an FPGA that would be easy to put on a board, you’d have to drop support for multiple voltage rails and thus multiple IO standards, which is exactly what you don’t want to lose. Building bitstreams is IMO not complicated. (I just copy a Makefile from a previous project and go from there.) Loading them is a matter of plugging in a JTAG cable and typing “mak…
> you’d have to drop support for multiple voltage rails and thus multiple IO standards, which is exactly what you don’t want to lose. Yes? Yes it is? 9 times out of 10, my entire board is LVCMOS33. I would love to have the option to drop all of the power rail complexity in a simplified series of parts. Sometimes you need maximum I/O speed. Sometimes you need maximum I/O flexibility. Sometimes you need processing hors…
> sometimes … sometimes … sometimes …
And sometimes you need support for multiple IO standards.
I don’t understand what point you’re trying to get across.
But if all you need is LVCMOS33, why do you not use a MAX10 FPGA with built-in voltage regulator? Or a similar FPGA device from GoWin that is positioned as a MAX10 alternative? What is wrong with those?
> JTAG
On our production line, we use JTAG to program the FPGA? We literally used the same “make program” command for development and production. That was for production volumes considerably larger than 100k.
> ISE
ISE was end of life’d when I started using FPGAs professionally. That was in 2012. The only reason it still exists is because some hold-outs are still using Spartan 6.
Re: FPGAs Need a New Future
#48Earlier quoted context omitted.
> you’d have to drop support for multiple voltage rails and thus multiple IO standards, which is exactly what you don’t want to lose. Yes? Yes it is? 9 times out of 10, my entire board is LVCMOS33. I would love to have the option to drop all of the power rail complexity in a simplified series of parts. Sometimes you need maximum I/O speed. Sometimes you need maximum I/O flexibility. Sometimes you need processing hors…
> often, what I actually need is just a little bit of weird logic that's asynchronous As a concrete example of this: two weeks ago I wanted a 21-input OR gate. It would have been wonderful if I could spend a little bit of money, buy a programmable thing in a 24-pin package, put it down, figure out some way to get the bitstream in (this is never pleasant in medium-volume manufacturing, so it's not like we're going to…
The device that you were looking was not an FPGA but a GAL22V10L.
Re: FPGAs Need a New Future
#49Earlier quoted context omitted.
> often, what I actually need is just a little bit of weird logic that's asynchronous As a concrete example of this: two weeks ago I wanted a 21-input OR gate. It would have been wonderful if I could spend a little bit of money, buy a programmable thing in a 24-pin package, put it down, figure out some way to get the bitstream in (this is never pleasant in medium-volume manufacturing, so it's not like we're going to…
The device that you were looking was not an FPGA but a GAL22V10L.
No, it wasn't. Those are mostly available in PLCC and DIP packages and even if you can get the SOIC/TSSOP versions they still cost $1.20 each at 10k volume. That's flat-out unacceptable for 99% of the things I do. The entire rest of the board I was talking about was $4.60. Processor included. $1.20 is not going to fly.
Re: FPGAs Need a New Future
#50Earlier quoted context omitted.
I've managed to make nice 'make' flows for Vivado, ISE, Quartus and DC. Libero took a bit more poking, but it's also possible. The GUI interfaces are what newcomers tend to aim for straight away, but they're not good for any long-term "repeatable" build flows and they're no use for CI. I think this is where a lot of the frustration comes from.
I think my real problem is that xilinx pushes the gui flows heavily. It is extremely annoying to configure the mpsoc fabrics entirely outside of vivado. Same thing for using any of their bundled IP.
Yes, IP usage is awkward and tricky. You can use the GUI to make the initial .xci file or .tcl file, but when you build a project, you need to use the same version of Vivado that the IP core was originally created in. Xilinx have improved that a little with 'write_ip_tcl' and 'write_bd_tcl' now having flags that let you ignore the version (or minor version). I've not had time to try those yet.