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Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

zeroasic.com

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Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#41

Post by tverbeure »

IshKebab wrote: post #33

When I looked into Yosys it very much seemed like a tool from the 80s that you pretty much had to be a Yosys developer to use. It still uses TCL scripting (which I know is standard in EDA but it shouldn't be). https://github.com/YosysHQ/yosys?tab=readme-ov-file#getting-... I wish we had a modern easy-to-use solution.

Yosys supports Python scripting.

I expect my synthesis tools to consume text and output a netlist and to be able to do that in regression with a Makefile. Is that eighties? Synopsys DC does it, so does Vivado and Quartus and any other synthesis tool, including Yosys.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#42

Post by amirhirsch »

robinsonb5 wrote: post #16
aappleby wrote: post #15

Earlier quoted context omitted.

"there's no publicly available documentation of the signal routing configuration or the bitstream format" Both of things either have already been reverse-engineered, or are in the process of being reverse-engineered.

The reverse engineering efforts are impressive (though as I understand it, limited to Xilinx series 7 and Cyclone V) but without robust and reliable timing data to go with the rest of the chip data, they can't give you the same level of confidence that a design will work across a range of a devices and operating conditions.

For the curious: the process of discovering the logic and route timings for an FPGA device is to use ring oscillators (three series inverters) and compare counters against a known clock. Place the inverters all over to test every LUT, and use every routing path to test each path's timing.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#43

Post by goku12 »

RossBencina wrote: post #30
topspin wrote: post #10

Earlier quoted context omitted.

How does that happen? When I see this, I suspect the vendor is operating under conditions that approach absolute chaos: dumping whatever junk someone imagines might be necessary into the stack with zero resistance, for years on end. Zero effort spent on any factoring that might threaten redundancy.

I'm not saying the tools aren't bloated, but I believe that a lot of the size (sorry, can't quantify right now) are the datasets for each and every FPGA model that the tool supports. This includes, among other things, timing information for every wire in the chip. You really only need the files for the device that you are targeting and you do have the option to install only that, or you can install larger groups (e.g…

Are you sure about that, or is it just a guess? If that is the case, how will the open source toolchains avoid the same problem when they eventually become the industry standard? (I can imagine something like a software repository for serving device-specific information on demand.) Are they planning anything right now?

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#44

Post by Aurornis »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

It's not that the official tools are the only way to work with parts.

It's that they're the only vendor supported method of working with the parts. If you build your product with an unsupported toolset and something doesn't work, you need to be prepared to reproduce the issue in the vendor support toolchain if you want support.

People coming from desktop and mobile development roll their eyes at this because they aren't coming across bugs in their x86-64 process or M1 Silicon that haven't already been patched over by some combination of microcode, the OS, and the toolchain. Everything works as expected.

Not so in the world of embedded. On modern complex systems, vendor involvement can be a critical part of the development process. Many of the products you have in your house like your router, Wifi gear, and IoT devices were probably co-developed to some degree with the hardware vendor. Starting with the vendor-provided reference design gets you to market much faster, even though you often could forge your own path with a separate toolchain and start from scratch.

It's still this way even in MCU development. You can go out and develop something like an STM32 system completely without STMicro's tools, but it's much easier to start the project in STMicro's tools and copy over the parts you need for setting up everything from clocks to peripherals, then to maintain a skeleton project in the official tools in case your separate toolchain starts acting funny.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#45

Post by rowanG077 »

adapteva wrote: post #34
rowanG077 wrote: post #26

Earlier quoted context omitted.

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC. https://github.com/zeroasiccorp/wildebeest

I think most people who seriously use Yosys already know that ABC is the foundation it’s built on. But let’s be real, this plugin is just twelve C++ source files. Calling that a “synthesis suite” just isn’t accurate. What it actually does is build on the synthesis suite provided by Yosys (and indirectly ABC), adding some extra algorithms and support for your FPGA family.

That said, this work is important, you do need it to get your FPGA running. And from the table, the reported optimizations look good (though I haven’t dug into them in detail). Still, describing it as “a synthesis suite” when it’s really “a plugin that adds FPGA support and a few optimizations to Yosys” does indeed leave me with a bad taste in my mouth.

Of course, you don’t have to agree with me. It’s clear from other comments that not everyone does, and that’s totally fine.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#46

Post by kragen »

This sounds exciting, and the press release does a great job of explaining why.

For anyone else who was wondering, it says it's under the Apache 2.0 license: https://github.com/zeroasiccorp/wildebeest?tab=Apache-2.0-1-...

I didn't realize that Xilinx xc7 synthesis was officially a feature of Yosys already!

Dropping the logic depth for picorv32 on LUT6s from 17 to 6 seems like it will double the achievable frequency or more. It's especially impressive that this beats the vendor tools—but it's unclear to me if this is an apples-to-apples comparison.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#47

Post by f1shy »

st_goliath wrote: post #8
dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

> ... don't require absurdly bloated development environments. Outside hobbies, I've been mostly away from this field for little over a decade by now. Is it still that bad? I remember back then, every single professional electronics engineer that I met had this die hard belief that this was simply how things work: You want to use DerpSemi micro controllers? You must install DerpStudio '98! Not the later 2005 version…

> Is it still that bad?

IMHO yes, if not worse.

Working now with some advanced devices from Xilinx (using very expensive top-line SoC. If you change version of the Vivado tools, you have to basically start again from 0 your project. Is a complicated mess because of matching of the OS in the ARM controller and the FPGA part…

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#49

Post by adapteva »

amluto wrote: post #39
someguydave wrote: post #38

Earlier quoted context omitted.

ah so this is misdirection - what they are really showcasing is their own new FPGA asic

They’re showcasing their open-source stack, built on existing tools, for their own FPGA. Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it woul…

Thank you, comment made my day:-)

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#50

Post by rowanG077 »

elsjaako wrote: post #28
rowanG077 wrote: post #26

Earlier quoted context omitted.

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I think we're reading the same article differently. They start out by describing all the work that has been done by other people to make open source synthesis possible. Then they say they've added some well known, industry standard optimizations to the existing open source tools. In addition, they made use of the abc tool in a way that maybe wasn't being done much before. My view is that if you think someone taking y…

I'm not a yosys developer to be clear, so I have no say what they license their software as. But indeed someone taken an open source software with a good community and re-branding it as their own while adding a thinly veiled lick of paint without even attempting to work together with upstream indeed leaves a bad taste in my mouth. On the other hand licensing software as GPL also leaves a bad taste in my mouth.
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