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The most unhinged AVX-512 instruction is GF2P8AFFINEQB.
https://www.youtube.com/watch?v=r_pPF5npnio&t=3300 (55:00)
"This is an instruction that doesn't exist in any computer right now, so why should I put it in a machine, if it's supposed to be realistic? Well, it's because it's ahead of time."
The most unhinged AVX-512 instruction is GF2P8AFFINEQB.
Here is Knuth introducing the MMIX instruction MXOR, which Intel later defined on vector registers under the name vgf2p8affineqb. https://www.youtube.com/watch?v=r_pPF5npnio&t=3300 (55:00) "This is an instruction that doesn't exist in any computer right now, so why should I put it in a machine, if it's supposed to be realistic? Well, it's because it's ahead of time."
Earlier quoted context omitted.
It has a fixed polynomial, so not really that useful for anything but AES The only case where I've had use of GF(2^8) inverses is in FEC algorithms (Forney's algorithm) and then you need some kind of weird polynomial. But all of those needs are rarely in the hot-path, and the FEC algo's are way outdated
I think the AFFINE and AFFINEINV instructions are specifically for FEC and maybe compression algorithms. I also think they smell like something requested by one of the big customers of Intel (e.g. the government).
The blog post mentions it as one of the reasons for the inefficiency of the conventional algorithm.
A glance at the algorithm shows that the recursion in question is a tail call. This means that any overhead can be readily eliminated using a technique known for nearly fifty years already.
Steele, Guy Lewis (1977). "Debunking the "expensive procedure call" myth or, procedure call implementations considered harmful or, LAMBDA: The Ultimate GOTO". Proceedings of the 1977 annual conference on - ACM '77.
Spoiler if you don’t want to read through the (wonder but many) paragraphs of exposition: the instruction is `vp2intersectq k, zmm, zmm`.
Not just that, but the fact that Intel CPUs execute it 20-30 times slower than AMD Zen 5 CPUs. Also, the fact that it's deprecated by Intel.
Earlier quoted context omitted.
And, as noted in the article, that's an instruction which only works on two desktop CPU architectures (Tiger Lake and Zen 5), including one where it's arguably slower than not using it (Tiger Lake). Meaning... this entire effort was for something that's faster on only a single kind of CPU (Zen 5). This article is honestly one of the best I've read in a long time. It's esoteric and the result is 99.5% pointless object…
Presumably Zen 5 cores will also get used in Threadripper and EPYC processors.
It might be an esoteric feature today. But if it'll become an ubiquitous feature in a few years, its nice to learn about using it.
Fascinating blog post. Having said that, it may seem like nitpicking but I have to take issue with the point about recursion, which is often far too easily blamed for inefficiency. The blog post mentions it as one of the reasons for the inefficiency of the conventional algorithm. A glance at the algorithm shows that the recursion in question is a tail call. This means that any overhead can be readily eliminated using…
Earlier quoted context omitted.
They had to disable AVX-512 only because Microsoft was too lazy to rewrite their thread scheduler to handle heterogeneous CPU cores. The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft…
Windows can work without SMM, especially NT - the problem is that SMM was created for a world where majority used DOS and the idea of using OS services instead of every possibly quirk of IBM PC was anathema to developers. Thus, SMM, because there was no other way to hook power management on a 386 laptop running " normal" DOS
Earlier quoted context omitted.
> It's a shame that Intel seemed to really not want people to use it AVX-512 was never part of the specification for those CPUs. It was never advertised as a feature or selling point. You had to disable the E cores to enable AVX-512, assuming your motherboard even supported it. Alder Lake AVX-512 has reached mythical status, but I think the number of people angry about it is far higher than the number of people who e…
They had to disable AVX-512 only because Microsoft was too lazy to rewrite their thread scheduler to handle heterogeneous CPU cores. The Intel-AMD x86-64 architecture is full of horrible things, starting with the System Management Mode added in 1990, which have been added by Intel only because every time Microsoft has refused to update Windows, expecting that the hardware vendors must do the work instead of Microsoft…