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Testing Generative AI for Circuit Board Design

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Re: Testing Generative AI for Circuit Board Design

#43
post #23

Earlier quoted context omitted.

I doubt it too, but I notice that I keep underestimating the models. Do you have a challenge task I can try? What's the easiest thing I could get an LLM to do for circuit board design that would surprise you?

Make two separate signals arrive at exactly the same time on two 50 ohm transmission lines that start and end next to each other and go around a right hand bend. At 3.8GHz. Edit: no VSWR constraint. Can add that later :) Edit 2: oh or design a board for a simple 100Mohm input instrumentation amplifier which knows what a guard ring is and how badly the solder mask will screw it up :)

It would seem to me that the majority of boards would be a lot more forgiving. Are you saying you wouldn't be impressed if it could do only say 70% of board designs completely?

Re: Testing Generative AI for Circuit Board Design

#45

This feels like an excellent demonstration of the limitation of zero-shot LLMs. It feels like the wrong way to approach this. I'm no expert in the matter, but for "holistic" things (where there are a lot of cross-connections and inter-dependencies) it feels like a diffusion-based generative structure would be better-suited than next-token-prediction. I've felt this way about poetry-generation, and I feel like it migh…

> This feels like an excellent demonstration of the limitation of zero-shot LLMs. It feels like the wrong way to approach this.

There is one posted on HN every week. How many more do we need to accept the fact this tech is not what it is sold at and we are bored waiting for it get good? I am not say "get better", because it keeps getting better, but somehow doesn't get good.

Re: Testing Generative AI for Circuit Board Design

#46

The conclusions are very optimistic given the results. The LLMs: * Failed to properly understand and respond to the requirements for component selection, which were already pretty generic. * Succeeded in parsing the pinout for an IC but produced an incomplete footprint with incorrect dimensions. * Added extra components to a parsed reference schematic. * Produced very basic errors in a description of filter topologie…

Yes, this seemed pretty striking to me: the author clearly wanted the LLM to perform well. They started with a problem for which solutions are pretty much readily available on the internet, and then provided a pretty favorable take on the model's mistakes.

But the bottom line is that it's a task that a novice could have solved with a Google search or two, and the LLM fumbled it in ways that'd be difficult for a non-expert to spot and rectify. LLMs are generally pretty good at information retrieval, so it's quite disappointing.

The cookie thing... well, they learn statistical patterns. People on the internet often try harder if there is a quid-pro-quo, so the LLMs copy that, and it slips past RLHF because "performs as well with or without a cookie" is probably not one of the things they optimize for.

Re: Testing Generative AI for Circuit Board Design

#47

This feels like an excellent demonstration of the limitation of zero-shot LLMs. It feels like the wrong way to approach this. I'm no expert in the matter, but for "holistic" things (where there are a lot of cross-connections and inter-dependencies) it feels like a diffusion-based generative structure would be better-suited than next-token-prediction. I've felt this way about poetry-generation, and I feel like it migh…

I agree diffusion makes more sense for optimizing code-like things. The tricky part is coming up with a reasonable set of "add noise" transformations.

> The tricky part is coming up with a reasonable set of "add noise" transformations.

Yes, as well as dealing with a variable-length window.

When generating images with diffusion, one specifies the image ahead-of-time. When generating text with diffusion, it's a bit more open-ended. How long do we want this paragraph to go? Well, that depends on what goes into it -- so how do we adjust for that? Do we use a hierarchical tree-structure approach? Chunk it and do a chain of overlapping segments that are all of fixed-length (could possibly be combined with a transformer model)?

Hard to say what would finally work in the end, but I think this is the sort of thing that YLC is talking about when he encourages students to look beyond LLMs. [1]

* [1] https://x.com/ylecun/status/1793326904692428907

Re: Testing Generative AI for Circuit Board Design

#48

Earlier quoted context omitted.

Update: Sonnet 3.5 is better than any other model for the circuit design and part finding tasks. Going to iterate a bit on the prompts to see how much I can push the new model on performance. Figures that any article written on LLM limits is immediately out of date. I'll write an update piece to summarize new findings.

That name threw me for a loop. 'Sonnet' already means something to EEs ( https://www.sonnetsoftware.com/ ).

[deleted]

Re: Testing Generative AI for Circuit Board Design

#49
post #8

Using neural networks to solve combinatorial or discrete problems is a waste of time imo, but I'd be more than happy if somebody could convince me of the opposite.

There are recent papers based on diffusion that perform quite well. Here's an example of a recent paper https://arxiv.org/pdf/2406.01661 . I am also working on ML-based CO. My approach has a close 1% gap on hard instances with 800-1200 nodes and less than 0.1% for 200-300 nodes on Maximum Cut, Minimum Independent Set, and Maximum Clique problems. I think these are very promising times for neural network-based discret…

Thanks, will try to give it a read this weekend. Would you say that diffusion is the architectural change that opened up CO for neural nets? Haven't followed this particular niche in a while

Re: Testing Generative AI for Circuit Board Design

#50
post #20

Earlier quoted context omitted.

I doubt it'd work any better. Most of EE time I have spent is swearing at stuff that looked like it'd work on paper but didn't due to various nuances. I have my own library of nuances but how would you even fine tune anything to understand the black box abstraction of an IC to work out if a nuance applies or not between it and a load or what a transmission line or edge would look like between the IC and the load? Thi…

Really? Most of the time? I find I spend an enormous amount of time on boring stuff like connecting VCC and ground with appropriate decoupling caps, tying output pins from one IC to the input pins on the other, creating library parts from data sheets, etc. There's a handful of interesting problems in any good project where the abstraction breaks down and you have to prove your worth. But a ton of time gets spent on t…

"Looks like you forgot pullups on your i2c lines" would be worth a big monthly subscription hahaha.
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