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Canon aims to ship low-cost 'stamp' machine this year to disrupt chipmaking

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Re: Canon aims to ship low-cost 'stamp' machine this year to disrupt chipmaking

#41

Post by VMG »

RetroTechie wrote: post #28
treffer wrote: post #13

Earlier quoted context omitted.

Most SOCs are trimmed for cost, which means cheap manufacturing. Especially the system on a chip design for single board computers. Even RPI5s with the Broadcom BCM2712 which is super high volume is 16nm. If they manage to get 5nm in 2026 at low cost than that's the path to take the SOC crown. This could even lead to RISC-V SOCs/SBCs at RPI power and price tag (yeah, still dreaming).

Energy efficiency, high performance, low cost per IC: pick 2.

When I compare my phone with a PDP11 it seems obvious that I can pick all three and then some

Re: Canon aims to ship low-cost 'stamp' machine this year to disrupt chipmaking

#42

Post by formerly_proven »

rjzzleep wrote: post #37
formerly_proven wrote: post #33

Earlier quoted context omitted.

Oh and just to clarify, by "Nikon chose to not pursue EUV" I of course mean "the US made sure the japs can't access the relevant technology because they were market leaders at the time".

Do you have in references for the US involvement in Nikon's decision to drop EUV?

https://brie.berkeley.edu/sites/default/files/wp118.pdf

Re: Canon aims to ship low-cost 'stamp' machine this year to disrupt chipmaking

#43

Post by snapplebobapple »

VMG wrote: post #41
RetroTechie wrote: post #28

Earlier quoted context omitted.

Energy efficiency, high performance, low cost per IC: pick 2.

When I compare my phone with a PDP11 it seems obvious that I can pick all three and then some

You are comparing time series data when the statement was obviously meant about cross sectional data.

Re: Canon aims to ship low-cost 'stamp' machine this year to disrupt chipmaking

#44

Post by fennecfoxy »

raverbashing wrote: post #17

Makes sense While everybody is looking at the SOTA factories, manufacturing is still constrained at the bigger nodes, and bringing the cost down at older processes looks like a worthy goal

Yeah, I definitely think it's worth pushing the boundaries at the far end, but the middle end it would be so cool to see dramatic evolution/price reductions there such that anybody could get an asic made (in a very large stamped node) a la PCBWay/Oshpark services almost.

Also keen to see us build silicon up into the 3rd dimension as far as we can, not stacking chips but just continuing to add more and more layers until z = x = y, similar to 3d printing I suppose, leading edge nodes don't really have the wiggle room for that sort of experimentation.

But a 20mm^2 multi-layer but "flat/traditional" 3nm chip vs a 20mm^3 50nm chunk of silicon layers would be super cool to play with!

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