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Why does CPU=8 in Intel Core i9-12900K have fast access to all other cores? It is interesting.
Possibility related to what fab generation the CPU is on vs. other chips tested?
EDIT: why the downvotes?
If anyone is interested, here are the results on my M1 Pro running Asahi Linux: Min: 48.3 Max: 175.0 Mean: 133.0 I’ll try to copy the exact results once I have a browser on Asahi, but the general pattern is most pairs have >150ns and a few (0-1; 2-3,4,5; 3-4,5; 4-5; 6-7,8,9; 7-8,9; 8-9) are faster at about 50ns. Edit: The results from c2clat (a little slower, but the format is nicer) are below. CPU 0 1 2 3 4 5 6 7 8…
Would love to see what the results are for an m2.
0 1 2 3 4 5 6 7
0
1 46±4
2 37±4 34±4
3 37±3 38±4 38±3
4 34±4 34±4 34±4 37±4
5 37±4 37±4 37±4 34±4 34±4
6 38±4 34±4 37±4 34±4 34±4 37±4
7 37±4 34±4 37±4 37±4 38±4 37±4 34±4It would be interesting to have a more detailed understanding of why these are the latencies, e.g. this repo has ‘clusters’ but there is surely some architectural reason for these clusters. Is it just physical distance on the chip or is there some other design constraint? I find it pretty interesting where the interface that cpu makers present (eg a bunch of equal cores) breaks down.
Rings are great for latency on low core count situations. The LCC Intel chips all have a massive 512-bit ring bus (2x256-bit in each direction) internally which delivers crazy fast core to core latency. However, this quickly starts to break down under higher core counts. Intel gets around this to some extent with its P and E cores with 4 E cores occupying the same slot on the ring bus as a P core. However, once you s…
Why does CPU=8 in Intel Core i9-12900K have fast access to all other cores? It is interesting.
Could it be because it's the newest CPU included in the test suite. Possibility related to what fab generation the CPU is on vs. other chips tested? EDIT: why the downvotes?
Earlier quoted context omitted.
SMT is usually disabled in these situations to prevent it from being a concern.
Maybe 10 years ago that as the common things, but there are so many exta resources (esp registers) that is is now giving up almost half the chip. If you can be cache friendly enough, the extra cycles will make up for it.
The only thing that matters at that point is latency, and unless you are cache-friendly enough to store your entire program in a single core's cache twice over, you would be better off disabling SMT altogether. And even if you were able to do that, it would not matter as a single thread would be done processing a message by the time the next one comes in. At least at the currently standard 10-25Gbps that the exchanges can handle.
In HFT, we're fine giving up half the registers in a core if it means we get an extra few microseconds of latency back.
Why does CPU=8 in Intel Core i9-12900K have fast access to all other cores? It is interesting.
Earlier quoted context omitted.
Could it be because it's the newest CPU included in the test suite. Possibility related to what fab generation the CPU is on vs. other chips tested? EDIT: why the downvotes?
I mean why CPU=8, not CPU=7 or CPU =9 has the fastest access. Anyway, I have asked this in [stackoverflow]( https://stackoverflow.com/questions/73767563 ) and get downvotes too. T_T
