41–50 of 87 posts
HBM might be an interesting idea. I would love to see multiple bandwidth levels of memory becoming a norm, with computers a very fast small amount of memory, and a larger set of DRR4 or DRR5. We already have multiple levels of cache, why not having multiple levels of RAM? Operating systems and software would need to accommodate a new reality where NUMA is the norm though. But it’s good that we even have the concept o…
Earlier quoted context omitted.
Almost everything in a car has a number of chips. Power regulations, communication buses... and in electric cars with thousands of batteries, at least one chip per battery for protection.
Electric cars have ONE battery with thousands of *cells*. I do realize that the colloquial term for "cell" is "battery" (ex: an AA cell is called a battery), but it becomes important to be precise with our words when talking about manufacturing. Small scale Li-ion does a protection-IC per cell (ex: cell phones), mostly because cell phones are so small they only use one cell. Larger scale Li-ion, such as Laptop batter…
> At electric-car scales, you have thousands-and-thousands of cells. You can't just manage all of them with one IC, so you build an IC per bundle. Maybe 48 cells or 100-cells per IC or so.
Ah okay, I had more expected something on the order of 1 IC per 4 cells to allow individual cell health monitoring.
How did SiFive get anywhere near 5nm TSMC?
They pay money just like any other customer of TSMC. SiFive has a lot of buzz in the industry. I wouldn't be surprised that TSMC wanted to work with them. But there are other intermediary companies that help startups group multiple chips from multiple companies together into a single mask. This is called a "shuttle" and allows the companies to split the costs of the masks (I've heard up to $30 million for 5nm) SiFive…
Earlier quoted context omitted.
Electric cars have ONE battery with thousands of *cells*. I do realize that the colloquial term for "cell" is "battery" (ex: an AA cell is called a battery), but it becomes important to be precise with our words when talking about manufacturing. Small scale Li-ion does a protection-IC per cell (ex: cell phones), mostly because cell phones are so small they only use one cell. Larger scale Li-ion, such as Laptop batter…
Indeed yes I meant cells, I'm not a native English speaker. > At electric-car scales, you have thousands-and-thousands of cells. You can't just manage all of them with one IC, so you build an IC per bundle. Maybe 48 cells or 100-cells per IC or so. Ah okay, I had more expected something on the order of 1 IC per 4 cells to allow individual cell health monitoring.
You're doing fine. Native English speakers don't know the difference between cell or battery either. This is more of a precise / technical engineering distinction.
* 9V Battery (https://imgur.com/FHJdhIK), a collection of 6x cells.
* AAAA Cell (one singular chemical reaction of 1.5V)
Notice that the imgur is wrong: they call it a AAAA battery (when the proper term is a AAAA cell).
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"Battery" is a bunch of objects doing one task. Originally, a "battery" described cannons. Or two rooks (in chess) that work together. Or... 6x 1.5V cells working together to produce a 9V battery.
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A lot of chips are made on mature fab lines because they don't need the performance of 5nm lines or can't justify the mask costs. No one is investing in mature fab lines because they're not leading edge and they're being run to amortize the initial investmnet made into them years ago. Therefore not much additional capacity for mature lines. So yes you can see 5nm chips being taped out but the 40-130nm chips are squee…
> A lot of chips are made on mature fab lines because they don't need the performance of 5nm lines or can't justify the mask costs. Alternatively: they're car-scale products dealing primarily with high electric currents (10s or 100s of milliamps) and/or higher voltages (5V instead of 1.3V). Smaller chips use (and therefore output) less current than larger scale chips. But if your goal is to output 10mA to better driv…
They're built using much larger feature sizes but on completely separate lines.
Earlier quoted context omitted.
A lot of chips are made on mature fab lines because they don't need the performance of 5nm lines or can't justify the mask costs. No one is investing in mature fab lines because they're not leading edge and they're being run to amortize the initial investmnet made into them years ago. Therefore not much additional capacity for mature lines. So yes you can see 5nm chips being taped out but the 40-130nm chips are squee…
Your point is valid, but this is almost certainly a shuttle run, so it won't be even one full wafer.
IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.
Routers / Switches have extremely weird performance characteristics, and I think that's what SiFive is targeting with this chip. * HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which m…
Earlier quoted context omitted.
> A lot of chips are made on mature fab lines because they don't need the performance of 5nm lines or can't justify the mask costs. Alternatively: they're car-scale products dealing primarily with high electric currents (10s or 100s of milliamps) and/or higher voltages (5V instead of 1.3V). Smaller chips use (and therefore output) less current than larger scale chips. But if your goal is to output 10mA to better driv…
High voltage MOSFETs and IGBTs are built on a completely different process. Size is definitely not an issue with them. It is about exotic doping to create the desired characteristics. They're built using much larger feature sizes but on completely separate lines.
Its not that the IGBT / MOSFETs are built on these microcontrollers. Its that the Gate-Driver can be integrated into a microcontroller (simplifying the circuit design and reducing the number of parts you need to buy).
Under normal circumstances, a microcontroller can probably source/sink 1mA (too little to adequately turn on an IGBT). You amplify the 1mA with a gate-driver chip into 100mA, and then the amplified 100mA is used to turn on/off the IGBT.
By integrating a gate-driver into the microcontroller, you save a part.
What is the use case of this chip? I have the feeling it is some way away from a general purpose CPU / SOC like the Apple M1?
> The SoC can be used for AI and HPC applications and can be further customized by SiFive customers to meet their needs. Meanwhile, elements from this SoC can be licensed and used for other N5 designs without any significant effort.
> The SoC contains the SiFive E76 32-bit CPU core(s) for AI, microcontrollers, edge-computing, and other relatively simplistic applications that do not require full precision.