It was unclear if "v8" of the MIPS architecture is a re-branded RISC-V or if v8 MIPS is a combined RISC-V + MIPS or what.
MIPS Becomes RISC-V
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Re: MIPS Becomes RISC-V
#42I just read the official statement[1] that's linked to in the article. Just so I get this straight: Wave Computing, the company that bought the remains of MIPS, is now (after bancruptcy) spinning it off as a separate company, that is going to work under the name MIPS, holds the rights to the MIPS architecture, but is doing RISC-V? [1] https://www.prnewswire.com/news-releases/wave-computing-and-...
That's what I got from it, but I have to say I don't understand the decision to throw away such a storied architecture as MIPS. I mean come on, the N64 runs on it!
PS1, PS2 and PSP also used MIPS processors and were each much more successful than the N64.
Re: MIPS Becomes RISC-V
#43This is huge. It looks like the only architectures widely-deployed in ten years will be x86, ARM, Power, and RISC-V (maybe also SPARC64 in Japan, although that's rare in the US).
This is indeed huge.
Should open the path for the modernization of the auto chip industry, according to [1], 80% of ADAS chips are based on mips.
[1] https://www.globenewswire.com/news-release/2019/02/28/174460...
Re: MIPS Becomes RISC-V
#44This is huge. It looks like the only architectures widely-deployed in ten years will be x86, ARM, Power, and RISC-V (maybe also SPARC64 in Japan, although that's rare in the US).
so basically the same architecutes that have been widely deployed for the past 20+ years?
Re: MIPS Becomes RISC-V
#45"Development of the MIPS processor architecture has now stopped" Is anyone still developing SPARC?
Gaisler and the ESA are launching SPARC into space.
Re: MIPS Becomes RISC-V
#46Everyone's right to celebrate the success of RISC-V, but part of me thinks it's a shame that there's relatively little architectural diversity ( edit I should have said ISA diversity ) in modern CPUs. MIPS, Alpha, and Super-H, have all but faded away. Power/PowerPC is still out there somewhere though. Apparently they're still working on SPARC, too. [0] At least we'll always have the PS2. ...until the last one breaks,…
What RISC-V achieves is architectural diversity over the boring mov, add, mul instructions: the interesting part is in vector and matrix manipulation, and while RISC-V is working on a great solution, it allows for other accelerators to be added.
Re: MIPS Becomes RISC-V
#47The progression of headlines is funny: 1) MIPS Strikes Back: 64-bit Warrior I6400 Arrives https://news.ycombinator.com/item?id=8258092 We are still in the game 2) Linux-running MIPS CPU available for free to universities – full Verilog code https://news.ycombinator.com/item?id=9444567 Okay, we are not doing so great, maybe we can get young kids hooked? 3) MIPS Goes Open Source https://news.ycombinator.com/item?id=187…
I have one of the purple MIPS SBCs from back when MIPS was briefly owned by Imagination ( https://en.wikipedia.org/wiki/Imagination_Creator https://elinux.org/MIPS_Creator_CI20 ). Slow as hell even back in 2014. I wonder if one day it'll be a museum piece :-?
I have a tube of IDT R3041s and R3051s. I remember using GCC compiled for a DECStation 2000 to write code for them. (I made a hand-held computer based on R3041).
I also have a tube of ARM 610s (VY86C060s I think) from the same project, but R3041 was PLCC, whereas ARM was fine pitch PQFP. PLCC was easier to deal with at the time...
Re: MIPS Becomes RISC-V
#48Earlier quoted context omitted.
The big innovation in architectures is in the SIMD world. AVX512 (x86 512-bit), SVE (ARM 512-bit), NVidia PTX / SASS (32x32-bit), AMD RDNA (32x32-bit), AMD CDNA (64x32-bit). 64-bit cores (aka: classic CPUs) are looking like a solved problem, and are becoming a commodity. SIMD compute however, remains an open question. NVidia probably leads today, but there seems to be plenty of room for smaller players. Heck, one maj…
Fujitsu seems like a leader for SIMD via their A64FX. I wonder if they will ever venture outside of the supercomputing niche.
SVE is looking like a general-purpose ARM instruction set in the future.
I believe the Neoverse V-cores (high-performance) will have access to the SVE instructions for example. So the SVE-SIMD is not necessarily locked to Fujitsu (though Fujitsu's particular implementation is probably crazy good. HBM2 + 512-bit wide and #1 supercomputer in the world and all...)
Re: MIPS Becomes RISC-V
#49If synthesisable MIPS cores from R3k to R20k enter the public domain, that would be something special. based on how previous such "announcements" have turned out, it's not gonna happen this time either.
Re: MIPS Becomes RISC-V
#50Earlier quoted context omitted.
> Is MIPS still a big enough name to make this much of a coup for RISC-V? Or is this the last ditch effort of a fallen star of the semi market? Mips has seemingly been on life support sine the late 90's. I kind of think the SGI buyout and later spin-off doomed them as they were focused on building high performance workstation processors while Arm was busy focusing on low power and embedded systems. Guess who was bett…
It's interesting that that's where they've been focused, because my only exposure to MIPS chips has been in low-cost Mikrotik routerboards, eg: https://mikrotik.com/product/RB450
MIPS was being used in set-top-boxes and media players as well, like https://www.imaginationtech.com/blog/dont-let-the-cpu-contro...