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New Transistor Structures At 3nm/2nm

semiengineering.com

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Re: New Transistor Structures At 3nm/2nm

#41

Post by ksec »

everdrive wrote: post #10

What is the benefit of smaller transistors? Serious question. Why does it matter if I have 7nm vs. 5nm vs. anything else?

> Serious question...

To Oversimplify.

With a Fixed Yield, and an exact 100% increase in Transistor Density that translate to 50% smaller Die Size.

On a Wafer, that would equate to Double the amount Die you have. All of a sudden your profits increase dramatically.

5nm also have a better power curve so within the same clock speed you have lower energy usage. Hence you can push for higher performance if needed.

The first point of Uni Economics is important for the industry. If you have high enough volume, say hundreds Million of chips per year then it make sense to move to the next node for cost saving. If you have small volume or low margin chip then the Design Cost, which is the most expensive part of chip making, would not work to your benefits.

And it also depends on Wafer price, If 5nm is Double the Price of 7nm then in the above example your unit cost would be exactly the same.

The second point is important for CPUs, and other things that are increasingly computational expensive like WiFi 6 and 5G Modem. You want your Smartphone to last longer on battery so they work better on an energy efficient node.

So basically it is a Cost / Performance trade offs.

Re: New Transistor Structures At 3nm/2nm

#42

Post by corty »

cactus2093 wrote: post #29
LatteLazy wrote: post #13

Earlier quoted context omitted.

Smaller means closer together. Closer together means less time for a signal to move from one to another. Less time means higher clock speeds. If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.

I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller an…

It is not wrong, it is rather correct. Speed of propagation in semiconductor materials is at most a third of speed of light in vacuum. So the distance travelled is rather limited for a signal. Also, a signal might have to traverse a few transistors or gates, so frequency in the 3GHz range does really limit processor sizes to the order of millimeters. You already said how to get around it: Pipelines, that limits the area a signal has to propagate. Also, one has to take care to make signals arrive early enough in the longest possible signal path as well as to distribute the clock in a way for it to arrive at aligned times everywhere, so you need a clock distribution net with known delays, etc. Chip timing is black art.

Re: New Transistor Structures At 3nm/2nm

#43

Post by Nokinside »

cactus2093 wrote: post #29
LatteLazy wrote: post #13

Earlier quoted context omitted.

Smaller means closer together. Closer together means less time for a signal to move from one to another. Less time means higher clock speeds. If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.

I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller an…

The speed of EM signal in copper is roughly 60% of the speed of light. You also have to account for timing jitter and wait until you are sure that everybody has the signal to prevent going out of sync. This means that reliable distance from a single clock is just a fraction of what the speed of signal theoretically allows.

Clock distribution networks use local clocks to buffer and amplify the global clock but they take a significant amount of chip area and make the chip larger. Clock distribution circuitry draws a significant amount of power. It can be 30-40% of the power usage. You want to use them as little as possible.

Re: New Transistor Structures At 3nm/2nm

#44

Post by mhh__ »

SpaceRaccoon wrote: post #40
adwn wrote: post #26

Earlier quoted context omitted.

> the speed of light is a bottleneck for processors It's not the speed of light [in a vacuum], but electric signal propagation speed in copper.

And the "electric signal" is an electromagnetic wave- also known as light. Nowhere did they imply the speed of light in a vacuum, the speed of light in copper is an equally valid interpretation.

That's true but it's easy to forget that the velocity factor of that wave is significantly smaller in (say) copper than air or a vacuum.

Re: New Transistor Structures At 3nm/2nm

#45

Post by mhh__ »

cactus2093 wrote: post #29
LatteLazy wrote: post #13

Earlier quoted context omitted.

Smaller means closer together. Closer together means less time for a signal to move from one to another. Less time means higher clock speeds. If you CPU is 100mm across, the speed of light limits it to 3GHz because that's how many times you can cross the cpu travelling at c. At 10mm you get 30GHz.

I don't really know enough to refute it, but this seems deeply and bizarrely wrong. It doesn't account for transistor count or density just the size of the entire chip? With pipelining I don't think a signal has to travel across the entire chip every cycle. It also doesn't really address the question above, since single core CPU speeds haven't increased in 15 years even though transistors have kept getting smaller an…

It's an approximation, or better a bound.

When designing chips or doing layout for FPGA designs, we do something called timing analysis to find out if signals get to where they should do such that the chip is stable ("meets timing").

There is a lot more to it than just distance. The transistors have speeds, to start with.

That and just because this size gives a bound on how quickly you can do things, the transistor count is also increasing, so the actual clock doesn't increase all that much.

Re: New Transistor Structures At 3nm/2nm

#46

Post by wallacoloo »

From what I can gather looking at the images and such, the device is one gate with 3 or more isolated channels, each with separate source/drains. Are these processes constrained such that all the sources/drains have to be linked together later? Or can they be used independently, allowing the designer to construct 3 or more transistors with a shared gate?

Re: New Transistor Structures At 3nm/2nm

#47

Post by femto113 »

everdrive wrote: post #10

What is the benefit of smaller transistors? Serious question. Why does it matter if I have 7nm vs. 5nm vs. anything else?

The numbers roughly correspond to the width of wires in the circuits, but the number of circuits you can fit per unit area depends on the square of that number so going from 7nm to 5nm roughly doubles density. The first microprocessor[1] was around 10,000nm so we're approaching 5,000x thinner wires or almost 25 million times more circuits (the latest Apple M1[2] is at 5nm have about 8,000,000x as many transistors as the 4004).

[1] https://www.intel.com/content/www/us/en/history/museum-story... [2] https://www.apple.com/newsroom/2020/11/apple-unleashes-m1/

Re: New Transistor Structures At 3nm/2nm

#48

Post by adwn »

SpaceRaccoon wrote: post #40
adwn wrote: post #26

Earlier quoted context omitted.

> the speed of light is a bottleneck for processors It's not the speed of light [in a vacuum], but electric signal propagation speed in copper.

And the "electric signal" is an electromagnetic wave- also known as light. Nowhere did they imply the speed of light in a vacuum, the speed of light in copper is an equally valid interpretation.

> And the "electric signal" is an electromagnetic wave- also known as light.

No, it's not. If it were, you'd have photons moving through your copper wire, which would be quite the sensation!

A moving electron does create a change in the electromagnetic field, however, so maybe that's where your confusion stems from?

Re: New Transistor Structures At 3nm/2nm

#49

Post by mng2 »

everdrive wrote: post #10

What is the benefit of smaller transistors? Serious question. Why does it matter if I have 7nm vs. 5nm vs. anything else?

Besides being able to pack more transistors into a given area, a smaller transistor has less gate capacitance (to first order). This means it can switch faster (smaller RC time constant) and less energy is expended in switching. Thus, going from generation to generation, the overall energy expenditure of a chip can be kept within a reasonable range despite adding many more transistors. You also may have heard of a "die shrink", where an existing design gets shrunk to the next technology node, using less power and clocking faster.

Shrinking isn't always a walk in the park though. Some nodes ago subthreshold leakage became a big problem until they figured out how to solve it.

Re: New Transistor Structures At 3nm/2nm

#50

Post by siver_john »

typon wrote: post #36
ur-whale wrote: post #28

One thing I've always wondered about when it comes to new process design at smaller scale: how much actual quantum mechanics is actually needed to get the job done? And ... if the answer is, as I suspect, a lot, what kind of numerical methods and processes are used to design and simulate these tiny quantum mechanical machines? [EDIT] I mean, when taking a basic QM course, there is a lot of contorsions to try and find…

Depends on what you mean by get the job done. (Rather which job) If you are doing research into designing advanced transistors with new geometry or new materials (which is what I did my graduate research in), you would be using something like DFT (Density functional theory) for equilibrium analysis and NEGF, Huckel theory etc. for simulating current. These methods only realistically work on ~500-1000 atom systems, be…

Just as a note, GPU supported code just now seems to be coming on line with like Quantum Espresso GPU version getting an alpha in 2019. I think a large part of that is due to the 64 bit precision making the speed up not as great on GPUs (and to a large extent eliminating the usage of consumer level cards which are popular at the classical molecular dynamics software like GROMACS). Plus Guassian, while having support since Kepler days note that earlier cards didn't have the memory requirements (which also is a huge problem for consumer cards) making adoption slower, because of the added costs.
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