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Clocking a 6502 simulator to 15GHz

scarybeastsecurity.blogspot.com

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Re: Clocking a 6502 simulator to 15GHz

#41

Post by halotrope »

dodo6502 wrote: post #37
halotrope wrote: post #21

After stumbling on Ben Eaters “Hello world from scratch” [1] I went out and bought the cpu some parts and breadboards. The chip is only a few dollars. It is highly recommended if you want to dive down into computers and digital logic on first principles. Also great fun to get a break from all the screens and layers upon layers of software that I have to deal with daily. 1. https://youtu.be/LnzuMJLZRdU

Kind of plugging my own project here, but I too am a software developer that found great joy from breaking away from all the layers of abstraction and working directly with the hardware. I created a portable game system with the 6502: http://www.dodolabs.io/

This is awesome!

Re: Clocking a 6502 simulator to 15GHz

#42

Post by jsd1982 »

To solve the FF page wrapping problem, I wonder if it would work to double-map each 6502 page to x64 host pages side by side. I assume the word read at FF would straddle the two mapped pages effectively reading the second byte at 00. You'd have to map to host page boundaries of course and probably offset all reads/writes to the end of the host page at $3F00.

Re: Clocking a 6502 simulator to 15GHz

#43

Post by abbeyj »

londons_explore wrote: post #11

It would be interesting to compare this project to simply converting 6502 assembly into LLVM IR, and letting clangs optimization passes work their magic. Obviously self modifying code would be hard to handle, but every other case ought to work, and the auto-vectorization ought to do amazing things to some loop-heavy code.

That's the approach taken by https://github.com/libcpu/libcpu. It supports 6502 and several other CPUs.

Re: Clocking a 6502 simulator to 15GHz

#46

Post by russellbeattie »

Huh... I hadn't considered it before, but Bender's brain could actually be a 6502, just being run at an insanely high clock speed. A few petahertz should be able to handle the AI involved, no?

Planck time is like 10^-43 seconds, so there's lots of room to divvy up a second for more processing power given advanced technologies...

Re: Clocking a 6502 simulator to 15GHz

#47

Post by nikanj »

baybal2 wrote: post #40
duskwuff wrote: post #33

Earlier quoted context omitted.

18 MHz, actually -- the FPGA clock speed is 73 MHz, but it executes the equivalent of one 6502 clock cycle in four of its clocks. That being said, this was implemented on a budget-line FPGA from 2006 (XC3S50A - a small Xilinx Spartan-3A). A modern performance-line FPGA would probably hit a couple hundred MHz easily.

It's still surprising how little relatively to the level of perceived performance have IPC count improved since seventies.

The perceived performance for an average desktop has been pretty stagnant since, I don't know, at least the mid-nineties.

Re: Clocking a 6502 simulator to 15GHz

#48

Post by spullara »

nikanj wrote: post #47
baybal2 wrote: post #40

Earlier quoted context omitted.

It's still surprising how little relatively to the level of perceived performance have IPC count improved since seventies.

The perceived performance for an average desktop has been pretty stagnant since, I don't know, at least the mid-nineties.

Softare expands to fill the CPU available.

Re: Clocking a 6502 simulator to 15GHz

#49

Post by cmrdporcupine »

baybal2 wrote: post #40
duskwuff wrote: post #33

Earlier quoted context omitted.

18 MHz, actually -- the FPGA clock speed is 73 MHz, but it executes the equivalent of one 6502 clock cycle in four of its clocks. That being said, this was implemented on a budget-line FPGA from 2006 (XC3S50A - a small Xilinx Spartan-3A). A modern performance-line FPGA would probably hit a couple hundred MHz easily.

It's still surprising how little relatively to the level of perceived performance have IPC count improved since seventies.

It seems to me that computational throughput has improved exponentially, but latency for input tasks etc. has in fact worsened in many cases.

Re: Clocking a 6502 simulator to 15GHz

#50

Post by kabdib »

variaga wrote: post #27
paulmd wrote: post #15

Earlier quoted context omitted.

"until pins stop wiggling"?

The pins don't physically wiggle. "pins wiggling" is a common metaphor for "the voltage level on a pin is changing". As a signal driver is toggled at increasing frequencies ('cranking up the clock'), the signal amplitude (voltage difference between the 'high' and 'low' period) starts to drop. At a high enough frequency, the signal will be indistinguishable from noise and 'stops wiggling'.

I was actually thinking about catastrophic failure, as in something on the chip burning out and making the clock stop.

My guess is that they were probably cooling it with beer (or at least cold beer bottle bottoms) to get that last critical Mhz, before drinking the beer.

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