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AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

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Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#41

Post by PedroBatista »

undersuit wrote: post #29
lousken wrote: post #16

Meanwhile i9 9900k still has only 16 3.0 lanes ...

Intel just dropped a bunch of details about the actual competitor to EPYC, Cascade Lake AP. These server chips will have 48 PCI-E 3.0 lanes, still not anywhere near the EPYC's claimed amount, but definitely better than what they are selling to the niche high-end gamers.

They're losing market share but it's better to lose some market share than look desperate and nuke most of their business strategy and golden egg basket.

Sure people hate Intel for their practices, but they can afford to be hated because they still can milk the market for at least a couple of years. "No one ever got fired for buying Intel" is a great asset and they have the confidence they'll bounce back and offer at competing product "in the future".

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#42

Post by PedroBatista »

blattimwind wrote: post #38
velox_io wrote: post #7

Earlier quoted context omitted.

Yeah, that's why most PCIe M2 top out at around 3500 MB/s, I doubt it will take long to saturate 7 GB/s (or double that in RAID0). Either way, it's a heck of a lot of bandwidth!

While NVMe drives are becoming quite common in regular computers, sadly most software is ill-equipped to handle that sort of I/O bandwidth well. (I would blame OS interfaces for at least three fifths of that, though people who think using textual formats where the most fastest, least correctest parsers top out at 1.5-2 GB/s for bulk data also have their share of blame).

Software moves "slower" because hardware needs to exist 1st and needs to see a widespread adoption in order to justify the cost of development and continuous improvement, also only hardware companies have the expertise because, well, they are the ones who developed the thing.

Doing software actually costs a lot, and no one wants to spend that kind of money past the "good-enough" threshold if they don't have to.

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#43

Post by tlamponi »

eropple wrote: post #21
lousken wrote: post #16

Meanwhile i9 9900k still has only 16 3.0 lanes ...

AMD's been adding more PCIe lanes across their hardware lineup than Intel has to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen 2 2700X only has 20 lanes for 8 cores.

I mean more would be certainly great, but with 20 you can at least run a x16 GPU and a x4 NVMe SSD, which is for my personal setup perfectly OK, I cannot do that with 16 lanes.

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#44

Post by velox_io »

Patrick-STH wrote: post #25
consp wrote: post #2

Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.

Here is the easy example: A dual 100GbE NIC requires a PCIe Gen4 x16 slot to run both ports at full speed. Mellanox ConnectX-6 200GbE cards require either 2x Gen4 or 1x Gen5 slot for full dual port bandwidth. Most of the larger NVMEoF nodes we are seeing are using more than one 100GbE NIC. Enterprise SSDs will rapidly fill Gen4 x4 lanes later this year as we start to see them launch alongside more mainstream platform…

Hi Patrick,

Before we had M2/U2 NVMe drives, there were quite a few manufacturers making drives that plug straight into the PCIe bus where they could easily access the full 16 lanes, and they still can...

Intel seems to be the only ones making PCIe drives (Octane's are funny; they don't look fast only 2000 MB/s, although they do win on latency and random access). Anyway, there doesn't seem to be much demand for that speed, I guess it's a case that x4 U2/M2 are good enough.

Speaking of which.. I'm am surprised there isn't a similar network interface utilising PCIe with a low overhead protocol the same as NVMe does. Getting towards the point where a small number of machines could share memory and CPU's between machines. I know we have Infiniband but that has always come at quite a cost, mainly in supercomputers.

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#45

Post by deepnotderp »

consp wrote: post #2

Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.

Deep learning training, especially distributed training solutions can utilize greater pcie bandwidth.

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#46

Post by twotwotwo »

craftyguy wrote: post #20

>why the AMD EPYC “Rome” generation will likely see 160x PCIe Gen4 lanes plus likely additional lane(s) for a necessary function. Emphasis mine. This seems to be pure speculation, not 'news'.

Yeah:

> I did give AMD the heads-up that it would be going live just after the Cascade Lake launch. They did not sanction this article (indeed, they will not be overly excited to see it is live.)

That seems to justify some doubts.

PCIe 4.0 support has got to cost some die area/power, and not many PCI devices will support it at first. That might point towards starting with a mix of 3.0 and 4.0 lanes.

If they did upgrade all lanes, and some devices show up, could be cool for some bandwidth-hungry GPU and/or HPC-networking use cases. Or for servers that wanted to load up on any kind of compatible device (SSDs, whatever): you can fit more 4.0 x4 than 3.0 x8 anythings in a given number of lanes.

Still think we'll have to wait a gen, though.

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#47

Post by esaym »

kilo_bravo_3 wrote: post #14
consp wrote: post #2

Can someone enlighten me with some information about application requiring the full 16x PCIe gen4 bandwidth per slot (or 32x gen3 for that matter)? I can imagine some HPC GPU solutions but other than that what requires the thoughput? There is obviously a market for this as both giants are building platforms.

Off the top of my head this would be great for massive enterprise VDI installations and game streaming services (which is just VDI by another name), ML, AI applications, and NVMe storage. Personally, this will be good for me because everything I do is bandwidth-starved. I'm not a radar scientist but I am a systems engineer supporting radar scientists working on air- and space-based Synthetic Aperture Radar (SAR) syst…

I've never heard of "SAR", that's very interesting... But I am curious, if the data truly comes from only radar, why are shadows apparent in many of the created images? Or does the same surface reflect radio waves differently based on whether it is in the sun or not?

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#48

Post by kllrnohj »

tlamponi wrote: post #43
eropple wrote: post #21

Earlier quoted context omitted.

AMD's been adding more PCIe lanes across their hardware lineup than Intel has to be sure, but EPYC is server-class stuff with 64 cores to a chip. The Ryzen 2 2700X only has 20 lanes for 8 cores.

I mean more would be certainly great, but with 20 you can at least run a x16 GPU and a x4 NVMe SSD, which is for my personal setup perfectly OK, I cannot do that with 16 lanes.

The chipset just multiplexes and it's fine. You're unlikely to actually use more than 16 lanes simultaneously in such a setup. But yes, Intel is being overly stingy with PCI-E lanes off of the CPU and leaning heavily on the chipset to compensate.

I'm hoping Ryzen 3rd gen bumps the lane count a bit more, otherwise Threadripper's 64 lanes look mighty nice...

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#49

Post by velox_io »

kllrnohj wrote: post #48
tlamponi wrote: post #43

Earlier quoted context omitted.

I mean more would be certainly great, but with 20 you can at least run a x16 GPU and a x4 NVMe SSD, which is for my personal setup perfectly OK, I cannot do that with 16 lanes.

The chipset just multiplexes and it's fine. You're unlikely to actually use more than 16 lanes simultaneously in such a setup. But yes, Intel is being overly stingy with PCI-E lanes off of the CPU and leaning heavily on the chipset to compensate. I'm hoping Ryzen 3rd gen bumps the lane count a bit more, otherwise Threadripper's 64 lanes look mighty nice...

The new Ryzens are meant to launch with PCIe 4.0 (this summer, I'm due an upgrade!), so effectively...

I'm surprised they don't come with more, especially many of the current ones come with 2-3 x16 slots, AND 2-3 M2s.. Both Intel and AMD have been adding more cores recently. Plus, if you're doing any GPU-based rendering, they're going to simultaneously move data back and forth from NVMe to the GPU's memory. But it grabs a headline and most synthetic benchmarks will only test RAM, graphics and storage in isolation - sneaky!

Re: AMD EPYC Rome 2P Will Have 128-160 PCIe Gen4 Lanes and a Bonus

#50

Post by Carropola »

esaym wrote: post #47
kilo_bravo_3 wrote: post #14

Earlier quoted context omitted.

Off the top of my head this would be great for massive enterprise VDI installations and game streaming services (which is just VDI by another name), ML, AI applications, and NVMe storage. Personally, this will be good for me because everything I do is bandwidth-starved. I'm not a radar scientist but I am a systems engineer supporting radar scientists working on air- and space-based Synthetic Aperture Radar (SAR) syst…

I've never heard of "SAR", that's very interesting... But I am curious, if the data truly comes from only radar, why are shadows apparent in many of the created images? Or does the same surface reflect radio waves differently based on whether it is in the sun or not?

Radar sends pulse. Radar moves. Radar looks at reflections from previous pulse. Because radar moved before waves returned and is now looking at the area from a different angle making the image appear illuminated from elsewhere. Its not the suns shadow but a radar shadow. Like if you took a picture with a flash and managed to reposition your camera to a different angle before the light from your flash reached the target.
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