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SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

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Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#41

Post by crankylinuxuser »

SloopJon wrote: post #38
ivoras wrote: post #37

Hmm, does it really have only 16 KiB of RAM or am I misinterpreting the spec? What would be the use case for a 320 MHz processor with 16 KiB RAM? Even ESP8266 has 80 KiB and runs at 80 MHz.

The only place I see that mentions 16 KB is the instruction cache on the S7 monitor core. Apart from cache, it doesn't look like any of these include RAM.

That's fairly standard. The problem there is going to be attaching ddr3 modules to a board. BGA is a pain in the ass for anything past 10x10 using a toaster oven. And for doing it "right" you really need xray QA.

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#42

Post by monocasa »

Posibyte wrote: post #20
PinkMilkshake wrote: post #10

I've only had a passing interest in learning assembly. It's always been in the "maybe one day" category. But after learning about how small the RISC-V instruction set is (less than 50 apparently, but I can't find a citation for that anywhere), I'm far more motivated to get into it.

I recommend the 6502[1] if you're just starting. What you learn applies almost everywhere, and it's very much a what-you-write-is-what-happens sort of processor. No branch prediction, no caches, no fancy features. Its op-set is very small and highly expressive. They still make them, in fact. That said, whether you choose to start with it or RISC-V, from personal experience SiFive's implementations are phenomenal. I u…

Having taught asm to people as their first language, I'd go with something like an MSP430. Since a 6502's registers are only half the pointer width, it really makes pointer manipulation more of a pain in the ass than it needs to be. That really obfuscates quite a.few.of the concepts that you're trying to learn by writing asm for a simple core.

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#44

Post by Iwan-Zotow »

thethirdone wrote: post #6
jbeard4 wrote: post #2

I am pretty excited about RISC-V. Hoping to see a v8 JavaScript and Node.js port in the future.

That shouldn't be super hard. I don't think there is much assembly in either. And C can be compiled to RISC-V already. My only experience porting node was to a specialized ARM system a while ago, so ARM support may have been already built in or things may have changed. edit: as people have commented, there indeed is a fair amount of arch specific stuff for reference the mips directory https://github.com/v8/v8/tree/ma…

> I don't think there is much assembly in either.

it has nothing to do with assembly, or ability to compile C

it is basically typical compiler with front-end and back-end. While front-end is platform independent and could be ported easily, back-end usually takes quite some time to retarget for a different architecture

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#45

Post by floatboth »

mrweasel wrote: post #22
zik wrote: post #11

Earlier quoted context omitted.

There are none yet. RISC-V is likely to appear in embedded and mobile devices before a full desktop machine is competitive with Intel processors.

It's most likely going to be like with ARM and be embedded only, sadly. There's a large number of us, not large enough though, that want a standard ATX motherboard, with PCI-Express and an ARM, RISC-V or PowerPC processor (well an affordable PowerPC).

MACCHIATObin is a mini-ITX ARMv8 board with PCIe and great firmware (comes with U-Boot but you can flash (or chainload from u-boot) EDK2/TianoCore with ACPI support (!) and even QEMU for the "GPU BIOS" thingy that lets you get video out as EFI framebuffer)

Also there's the SoftIron Overdrive 1000 (sold only as full system, not bare board)

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#47

Post by aidenn0 »

vhodges wrote: post #30
mrweasel wrote: post #22

Earlier quoted context omitted.

It's most likely going to be like with ARM and be embedded only, sadly. There's a large number of us, not large enough though, that want a standard ATX motherboard, with PCI-Express and an ARM, RISC-V or PowerPC processor (well an affordable PowerPC).

(A more) affordable PPC option is coming (though no pricing yet): https://wiki.raptorcs.com/wiki/Blackbird (mATX)

!! The Raptor workstation was just barely outside my budget; if I hadn't just upgraded my actual workstation I probably could have talked myself into it.

Assuming it's priced comparably cheaper to the raptor, I am buying a blackbird as soon as it comes out.

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#48

Post by Zeetah »

aidenn0 wrote: post #46

The M7 is an out-of-order processor, these all look to be in-order. Many artificial benchmarks (including Dhrystone) are very forgiving of in-order stages, so I would expect this to underperform relatively to a similarly benchmarked M7.

M7 is actually an in-order processor. It does have six-stage dual-issue pipeline.

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#49

Post by microcolonel »

aidenn0 wrote: post #46

The M7 is an out-of-order processor, these all look to be in-order. Many artificial benchmarks (including Dhrystone) are very forgiving of in-order stages, so I would expect this to underperform relatively to a similarly benchmarked M7.

Apparently good Cortex-M7s get around 5 CoreMark/MHz (NXP crossover, STM32H7), so it's almost identical per MHz, and I'm willing to bet that they can get higher frequencies with less effort (if you look at the SiFive MCUs, they run at stupid frequencies compared to similar competing cores, and were generally available almost two years ago now). For further comparison, the Broadwell Xeon I'm typing this on gets about 7.2 CoreMark/MHz (running at full turbo, 4GHz, on one core).

Re: SiFive Introduces 7 Series RISC-V Cores with E7, S7 and the U7 Series

#50

Post by aidenn0 »

Zeetah wrote: post #48
aidenn0 wrote: post #46

The M7 is an out-of-order processor, these all look to be in-order. Many artificial benchmarks (including Dhrystone) are very forgiving of in-order stages, so I would expect this to underperform relatively to a similarly benchmarked M7.

M7 is actually an in-order processor. It does have six-stage dual-issue pipeline.

Oh you're right. It has speculative execution, but is otherwise strictly in-order, my mistake.
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