Earlier quoted context omitted.
Traditional compiler techniques may have struggled with maintaining code for different architectures, but a lot has changed in the last 15 years. The rise of widely used IR languages has led to compilers that support dozens of architectures and hundreds of instruction sets. And they are getting better all the time. The compiler has nearly all of the information that the CPU has, and it has orders of magnitude more. A…
> At best, your CPU can think a couple dozen cycles ahead of what it is currently executing. The 200-sized reorder buffer says otherwise. Loads/stores can be reordered for 200+ different concurrent objects on modern Intel skylake (2015 through 2020) CPUs. And its about to get a bump to 300+ sized reorder buffers in Icelake. Modern CPUs are designed to "think ahead" almost the entirety of DDR4 RAM Latency, allowing re…
You get instructions scheduled based on actual dynamically measured usage patterns, but you don't pay for dedicated circuits to do it, and you don't re-do those calculations in hardware for every single instruction executed.
It's not a guaranteed win, but I think it's worth exploring.