Perfect for snooping on other people’s projects. No one in their right mind would touch this. It’s cheaper to buy the board yourself.
It seems to be a Linux Foundation project, my trust is implicit higher than what you're claiming. Why wouldn't you trust them? It's also aimed at open-source projects, for free, with the intent to improve RISC-V support.
The RISE RISC-V Runners: free, native RISC-V CI on GitHub
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Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#32Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#33Earlier quoted context omitted.
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough. The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
The RISC-V ISA can be fast. Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years. The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation). This should give you an idea about how fast RISC-V is improving.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#34Earlier quoted context omitted.
The RISC-V ISA can be fast. Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years. The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation). This should give you an idea about how fast RISC-V is improving.
I'd be pretty surprised if Ascalon actually hits Zen 5 perf (I'm gessing more like Zen2/3 for most real world workloads). CPU design is really hard, and no one makes a perfect CPU in their first real generation with customers. Tenstorrent has a good team, but even the "simple" things like compilers won't be ready to give them peak performance for a few years.
Certainly not in the Atlantis SoC, due to the older fab node used. Zen2-3 territory IPC is the expectation, with lower clocks than these actually got.
By the time they have the necessary scale to use the best fabs, they'll be tapping out something newer than the Ascalon that went into Atlantis.
Tenstorrent expects to reach parity with the best x86 and arm chips by 2028.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#35My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
The arrival of the first RVA23 chips, which is expected next month, will change the status quo. Besides RVA23 compliance, these are dramatically faster than earlier chips, enough for most people's everyday computing needs i.e. web browsing, video decoding and such. K3 got close to rpi5 per-core performance, but with more cores, better peripherals, and 32GB RAM possible, although unfortunately current RAM prices are n…
Alastor is something else; a core from Tenstorrent that is considerably smaller than Ascalon.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#36Earlier quoted context omitted.
It seems to be a Linux Foundation project, my trust is implicit higher than what you're claiming. Why wouldn't you trust them? It's also aimed at open-source projects, for free, with the intent to improve RISC-V support.
Why would you trust anyone offering free candies?
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#37Earlier quoted context omitted.
Some of that could be related to the ISA but I'm hoping that it's just the fact that the current implementations aren't mature enough. The vast majority of the ecosystem seems to be focused on uCs until very recently. So it'll take time for the applications processors to be competitive.
The RISC-V ISA can be fast. Tenstorrent Ascalon, expected later this year, is expected to be AMD Ryzen 5 speeds. Tenstorrent hopes to achieve Apple Silicon speeds in a few years. The SpacemiT K3 is about half as fast as Ascalon and available in April. K3 is 3-4 times faster than the K1 (previous generation). This should give you an idea about how fast RISC-V is improving.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#38Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#39Earlier quoted context omitted.
RISC-V microcontrollers are inexpensive but “application” processors will be expensive until volumes increase. Performance will get “good enough” over the next 2 years. Prices will drop after that.
That the "good enough" SoCs will be arriving "over the next 2 years" is what the RISC-V advocates have told us for quite a few years now.
The SpacemiT K3 has the multi-core performance of a 2019 MacBook Air and higher AI performance than an M4. That is better multi-core than an RK3588. If it were less expensive, the K3 would already be good enough for many people.
Alibaba has the C930 which is faster than the K3. We will see if it gets released to the rest of us.
Tenstorrent will release a chip in a few months that is twice as fast as the K3.
The recently announced C950 is supposed to be even faster but will be a year or more.
Of course, “good enough” is subjective but my statement was based on the above.
But you are right that there have been some false starts.
The SG2380 was just as fast as K3 and was ready to go two years ago. TSMC refused to manufacture it over US sanctions.
Ventana was about to release a very fast RISC-V chip but Qualcomm bought them.
Rivos was very close to releasing a RISC-V GPU but Meta bought them.
But even without these high-end chips, RISC-V is enjoying great success. It is taking over the microcontroller space. And billions of RISC-V cores are shipping.
Re: The RISE RISC-V Runners: free, native RISC-V CI on GitHub
#40My experience with RISC-V so far is that the chips are not much faster than QEMU emulation. In other words, it's very slow.
Particularly for my use case, Go cross compilation, QEMU and binfmt work really well together.
Still, for some things, it's nice to test on actual hardware.
Here's a workflow so you can see both approaches working: https://github.com/ncruces/wasm2go/blob/main/.github/workflo...