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Two Weeks Until Tapeout

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Re: Two Weeks Until Tapeout

#31

Post by tucnak »

caisley wrote: post #23
tucnak wrote: post #14

Earlier quoted context omitted.

I'm not OP, but perhaps you, or somebody else here, could answer my question, albeit one that is slightly off-topic. In the recent years, in part courtesy of cryptoindustry investment, there were many advancements in zero-knowledge mathematics and applied cryptography. I've been on-and-off researching computational approaches to liquid democracy[1], on the off-chance that we may one day apply it in my country, Ukrain…

Hey, I'm not a system-level digital designer, but for government-level initiatives to provide 130nm and 65nm fabs for public benefit, yes it exists! From the 2025 Free Silicon Conference: https://wiki.f-si.org/index.php?title=The_Transparent_Refere... https://wiki.f-si.org/images/e/eb/OpenFab%40FSiC2025.pdf The initiative started in Germany, where the research institute IHP already provides an open source 130nm PDK a…

Wow, thanks! I was completely unaware of it, of course.

Re: Two Weeks Until Tapeout

#32

Post by tucnak »

ajb wrote: post #30
tucnak wrote: post #20

Earlier quoted context omitted.

I previously came across OpenTitan, but it's hardware design only, right? It doesn't actually concern itself with bringing up transparent manufacturing process? For example, I couldn't find anything about the costs necessary to bring up a fab?

A project that addresses that issue is betrusted: https://betrusted.io/ Their plan for fab trust is not to bring up a fab,but to design for inspectability: https://bunnie.org/iris/

I happen to own a Precursor, and indeed used it for some experiments, but it's unfortunately limited by Xilinx Spartan-7 availability, which is one of the few FPGA's that have been reverse-engineered, and they probably don't make it anymore... Another one that has been RE'd is Lattice ECP5 but it's in the same category. I'm pretty sure you couldn't make 50 million devices like that. I know they've been looking into alternatives, but haven't caught up yet.

Re: Two Weeks Until Tapeout

#33

Post by lizknope »

caisley wrote: post #29
lizknope wrote: post #27

I've probably worked on 70 chips over the last 30 years. Tape out time always sucks. I'm in physical design which is fixing all the timing violations, DRC violations, LVS errors, and dealing with late design changes. Working 80 to 100 hours a week for a month really sucks and makes you wonder why you didn't go into software. When you combine it with a fixed shuttle date like in the article it is even worse because if…

Can I ask how often you guys end up doing gate-level netlist ECOs, instead of re-running synthesis when you're close to a deadline? Also, post-fabrication, if a mistake is found, have you been able to fix it just with a new M1 or M2 mask, instead of paying for a full new mask set?

If the change is under 1000 logic cells and no new flip flops then we do a it as an ECO. If there are tons of new flip flops we resynthesize and start over.

Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.

I've worked at one huge company where they planned 3 full base layer mask sets and 1-2 metal spins for each full base layer set. This was when doing a chip on a brand new process node where you couldn't always trust the models the fab gave you so you wanted more post silicon characterization to recalibrate models.

Re: Two Weeks Until Tapeout

#35

Post by random_duck »

lizknope wrote: post #33
caisley wrote: post #29

Earlier quoted context omitted.

Can I ask how often you guys end up doing gate-level netlist ECOs, instead of re-running synthesis when you're close to a deadline? Also, post-fabrication, if a mistake is found, have you been able to fix it just with a new M1 or M2 mask, instead of paying for a full new mask set?

If the change is under 1000 logic cells and no new flip flops then we do a it as an ECO. If there are tons of new flip flops we resynthesize and start over. Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of…

> The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine.

Oh, this is fascinating.

Re: Two Weeks Until Tapeout

#36

Post by random_duck »

caisley wrote: post #22
random_duck wrote: post #17

Earlier quoted context omitted.

Thanks for offering. Do you do analog design, and which market niche are you targeting: low cost per part or something else?

I work in custom CMOS image sensor design, targeting scientific imaging applications like electron microscopes, X-ray microscopy, and detectors for high-energy physics. Our designs aren't that cost sensitive from a unit cost perspective, because we are at most probably making several thousand of the chips. So the cost per chip can effectively range from 10-100$ at this scale, after yield losses. But the fixed costs o…

Oh thanks, this is really interesting. Is there a limit to how far you can scale down your node to build the full frame image sensor: is 180nm the largest feasible node?

Re: Two Weeks Until Tapeout

#37

Post by ajb »

tucnak wrote: post #32
ajb wrote: post #30

Earlier quoted context omitted.

A project that addresses that issue is betrusted: https://betrusted.io/ Their plan for fab trust is not to bring up a fab,but to design for inspectability: https://bunnie.org/iris/

I happen to own a Precursor, and indeed used it for some experiments, but it's unfortunately limited by Xilinx Spartan-7 availability, which is one of the few FPGA's that have been reverse-engineered, and they probably don't make it anymore... Another one that has been RE'd is Lattice ECP5 but it's in the same category. I'm pretty sure you couldn't make 50 million devices like that. I know they've been looking into a…

Their next one (https://baochip.com/) is going to be a SoC, piggy backed on another company's SoC. So not completely open source RTL, but enough to prove their technology on a larger scale. Bunnie's presentation of it is here: https://media.ccc.de/v/39c3-xous-a-pure-rust-rethink-of-the-... (25 minutes in)

Re: Two Weeks Until Tapeout

#38

Post by lizknope »

random_duck wrote: post #35
lizknope wrote: post #33

Earlier quoted context omitted.

If the change is under 1000 logic cells and no new flip flops then we do a it as an ECO. If there are tons of new flip flops we resynthesize and start over. Lots of chips have metal spins to fix errors. The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of…

> The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine. Oh, this is fascinating.

The other alternative is that you sprinkle spare gates around the chip. If the chip is 10mm x 10mm then every 100 microns you put a group of cells that just have their inputs tied to 0 and the outputs go nowhere. You put in a good mix of flip flops, and combinational logic cells. Then when you need to do a metal ECO the RTL team says "We need 2 AND gates, 1 OR gate, 1 mux, and they are connected to these 5 cells." So you highlight those 5 cells and find the closest spare logic group and use those.

The ECOFILLER gate array style cells are easier to use.

Then during the DRC check process in Calibre we run a check to make sure that the base layers stayed the same and only the metal layers changed. Since we have 18 metal layers in a leading edge node hopefully only metal layers 1 to 3 changed for the metal ECO so you only have to pay to make new versions of that.

A full mask set in 3nm can be over $30 million. Just a new set of metal masks is around $20 million.

A full mask run takes about 4 months in the fab. Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers. Then when you do a metal respin they get those out of storage and save a month.

Re: Two Weeks Until Tapeout

#39

Post by williadc »

I'm shocked that SRAMs would be considered a luxury item for open silicon. They're essential for building anything that would be commercially viable, since area is far from free.

Re: Two Weeks Until Tapeout

#40

Post by random_duck »

lizknope wrote: post #38
random_duck wrote: post #35

Earlier quoted context omitted.

> The blank areas of the chips are filled with filler cells but most of them are special "ECOFILLER" cells that are basically generic pairs of N/P transistors like a gate array. These can then be turned into any kind of cell just by using metal. They are a little slower but work fine. Oh, this is fascinating.

The other alternative is that you sprinkle spare gates around the chip. If the chip is 10mm x 10mm then every 100 microns you put a group of cells that just have their inputs tied to 0 and the outputs go nowhere. You put in a good mix of flip flops, and combinational logic cells. Then when you need to do a metal ECO the RTL team says "We need 2 AND gates, 1 OR gate, 1 mux, and they are connected to these 5 cells." So…

So you want to sprinkle the faster cell groups around, but the ecofiller gates are more flexible since they are everywhere by default ?

> Normally you tell the fab to keep a few wafers after the base layers and don't manufacture the metal layers.

Oh, I had no idea that was a thing.

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