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Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

zeroasic.com

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Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#31

Post by drob518 »

elsjaako wrote: post #28
rowanG077 wrote: post #26

Earlier quoted context omitted.

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I think we're reading the same article differently. They start out by describing all the work that has been done by other people to make open source synthesis possible. Then they say they've added some well known, industry standard optimizations to the existing open source tools. In addition, they made use of the abc tool in a way that maybe wasn't being done much before. My view is that if you think someone taking y…

Exactly. “You did what? You complied with my license terms?!?! How dare you!”

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#33

Post by IshKebab »

When I looked into Yosys it very much seemed like a tool from the 80s that you pretty much had to be a Yosys developer to use. It still uses TCL scripting (which I know is standard in EDA but it shouldn't be).

https://github.com/YosysHQ/yosys?tab=readme-ov-file#getting-...

I wish we had a modern easy-to-use solution.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#34

Post by adapteva »

rowanG077 wrote: post #26
elsjaako wrote: post #24

Earlier quoted context omitted.

When you release something as open source, a third party grabbing it and releasing it is explicitly something that can be done. I can't speak for them, so I'm not sure, but I feel like new FPGA suppliers coming around having open source tooling being the default is something that the authors of Yosys would like. Zero ASIC even credited the original authors in the press release and released the source code, which they…

There is obviously a difference between legality and what I would consider good behavior. I didn't say what they are doing is illegal. I just said it leaves a bad taste in my mouth. In essence this is something like 99% yosys + 1% their own sauce. Yet they market it as 99% their own sauce + 1% yosys.

I am sorry you that's how it looks...can't argue with feelings, We did everything we could to give credit. Open source SW should be a stack and every project needs a proper name as a reference. I do find the statement a bit ironic though, b/c 99% of Yosys users don't know that 99% of the logic synthesis sauce in Yosys is done by ABC.

https://github.com/zeroasiccorp/wildebeest

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#35

Post by adapteva »

imtringued wrote: post #22
adwn wrote: post #6

I don't understand the table under Benchmark Results . To compare the quality of two toolchains, the device architecture needs to be the same. "LUT6" vs "LUT4" doesn't cut it, there's much, much more to the architecture of an FPGA than the width of its look-up tables [1], and even for the "LUT6" category, I see four different devices. [1] Consequently, there's more to FPGA synthesis than LUT mapping, so take the repo…

Not just that, their device "z1060" doesn't exist outside this blog post. We literally don't know what it is.

Documentation can be found in two places. What else do you need to know?

https://github.com/siliconcompiler/logiklib/tree/main/logikl...

https://github.com/zeroasiccorp/wildebeest/tree/main/archite...

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#36

Post by adapteva »

adwn wrote: post #6

I don't understand the table under Benchmark Results . To compare the quality of two toolchains, the device architecture needs to be the same. "LUT6" vs "LUT4" doesn't cut it, there's much, much more to the architecture of an FPGA than the width of its look-up tables [1], and even for the "LUT6" category, I see four different devices. [1] Consequently, there's more to FPGA synthesis than LUT mapping, so take the repo…

Yeah, this was a big dilemman You can't compare two different compilers for two different hw targets. That would be like benchmarking GCC compiling to ARM with LLVM compiling to x86.

Thierry's synthesis scripts are really very clever, and the go way beyond our Platypus FPGA arch. We are realistic that until we have seilicon nobody cares about our arch. Releasing the work as open source, we think someone should adapt the code for all of the other targes I Yosys (xilinx, lattice...etc) so that everyone can benefit.

We contribute a lot of code to open source, but as an FPGA vendor we are not going to spend time/money optimizing compilers for our competitors:-)

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#37

Post by celegans25 »

boatfloatgoat wrote: post #32

will a smaller synthesis LUTs/logic depth result translate into smaller Map/P&R and higher fMax or not necessarily?

Often but not always. For most newer FPGAs, routing is the main source of delay on the critical path, not logic. So if the synthesis tool lowers the logic depth, but does so in a way that increases the distance the signal must travel on the chip, it likely won't help FMax.

This can be caused by increased logic usage, if the synthesis tool must create significantly more LUTs to reduce the critical path. This may make it harder to place the logic on the critical path close together, increasing the routing delay.

Additionally, if the synthesis tool replaces something with a dedicated routing path (most FPGAs have dedicated routing for carries, some may have dedicated routing for local connections in a CLB or between CLBs). These dedicated routing connections usually have a lower delay than the general purpose routing network, potentially increasing delay

The figures they have listed look promising though, they're lower or comparable to the commercial tools in terms of resource usage, with lower or comparable logic depths. They do however not have support for things like carry chains, which may potentially make some things like adders slower than the other tools.

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#38

Post by someguydave »

adapteva wrote: post #35
imtringued wrote: post #22

Earlier quoted context omitted.

Not just that, their device "z1060" doesn't exist outside this blog post. We literally don't know what it is.

Documentation can be found in two places. What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest/tree/main/archite...

ah so this is misdirection - what they are really showcasing is their own new FPGA asic

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#39

Post by amluto »

someguydave wrote: post #38
adapteva wrote: post #35

Earlier quoted context omitted.

Documentation can be found in two places. What else do you need to know? https://github.com/siliconcompiler/logiklib/tree/main/logikl... https://github.com/zeroasiccorp/wildebeest/tree/main/archite...

ah so this is misdirection - what they are really showcasing is their own new FPGA asic

They’re showcasing their open-source stack, built on existing tools, for their own FPGA.

Imagine if, 25 years ago, a company had designed a new CPU ISA and core and, as part of the development process, ported GCC and done a nice job tuning the existing optimization passes, with the intention of the GCC port being the primary toolchain that commercial users would use. They could write a blog post about it, and it would have been great. Maybe they even would have acknowledged in the blog post that the stack included binutils :)

Re: Zero ASIC releases Wildebeest, the highest performance FPGA synthesis tool

#40

Post by tverbeure »

dlcarrier wrote: post #2

The best part of open-source synthesis tools is that they don't require absurdly bloated development environments. The only thing I've encountered that's worse is Android Studio. Getting more efficient output is a nice bonus.

The installation can be around 100GB, which is a lot, but you have to distinguish the build part from the IDE. I hardly ever use the IDE and just use a Makefile.

The open source tools still lack too many features to be useful for non-hobby development.

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