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Test Results for AMD Zen 5

agner.org

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Re: Test Results for AMD Zen 5

#31

Post by crest »

Intralexical wrote: post #19
londons_explore wrote: post #15

> Integer vector instructions and floating point vector instructions now have the same latencies. There is very little reason to use integers for anything anymore. Loop counter? Why not make it a double - you never know when you might need an extra 0.5 loops at the end!

Integers aren't for performance. They're for precision (anything financial for example) and occasionally size.

At least historically integer operations also offered lower latency and higher throughput on CPUs. For decades integer addition and bitwise logical operations have been the canonical single-cycle instructions that any microarchitecture could perform at least once per cycle without visible latency while floating point operations and integer multiplication had multi-cycle latency if it was even fully pipelined.

Zen 5 breaks several performance "conventions" e.g. AMD went directly from one to three complex scalar integer units (multiplication, PDEP/PEXT, etc.).

Intel effectively has two vector pipelines and the shortest instruction latency is a single cycle while Zen 5 has four pipelines with a two cycle minimum latency. That's a *very* different optimisation target (aim for eight instead of two independent instructions in flight) for low level SIMD code going forward despite an identical instruction set.

Re: Test Results for AMD Zen 5

#32

Post by rft »

kklisura wrote: post #30

Are there any good resources on how does one obtain all of this information?

The linked PDF in the post contains a section on how the values are measured and a link to the test suite. Search in [1] for "How the values were measured". For another project that measures the same/very similar values you can check out [2]. They have a paper about the tool they are using [3].

There is also AMD's "Software Optimization Guide" that might contain some background information. [4] has many direct attachments, AMD tends to break direct links. Intel should have similar docs, but I am currently more focused on AMD, so I only have those links at hand.

[1] https://www.agner.org/optimize/instruction_tables.pdf

[2] https://www.uops.info/background.html

[3] https://arxiv.org/abs/1911.03282

[4] https://bugzilla.kernel.org/show_bug.cgi?id=206537

Re: Test Results for AMD Zen 5

#33

Post by monster_truck »

This matches my experience with Zen in basically any generation. Once you've used all of the tricks and exhausted all of the memory and storage bandwidth, you'll still have compute left.

It's often faster to use one less core than you hit constraints at so that the processor can juggle them between cores to balance the thermal load as opposed to trying to keep it completely saturated.

Re: Test Results for AMD Zen 5

#34

Post by bitmasher9 »

KetoManx64 wrote: post #26
heraldgeezer wrote: post #24

Earlier quoted context omitted.

Windows laptops? Desktops for gaming? AMD makes the best gaming CPUs with the X3D series.

What about actually doing something useful to bring prosuctive?

If I’m being productive I’d rather have an AMD chip than M4 so I can run Linux comfortably.

Re: Test Results for AMD Zen 5

#35

Post by adgjlsfhk1 »

ryao wrote: post #21
ashvardanian wrote: post #5

> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…

AMD CPUs tend to have more memory bandwidth than Intel CPUs and inference is CPU bound, so their claim seems accurate to me. Whether the core does a 512-bit write in 1 cycle or 2 because it is two 256-bit writes is immaterial. Memory bandwidth is bottlenecked by 64GB/sec per CCX. You need to use cores from multiple CCXs to get full bandwidth. That said, the EYPC 9175F has 614.4GB/sec memory bandwidth and should be ab…

you can use higher write bandwidth than the CCX bandwidth by having multiple writes that go to the same L2 address before going out to RAM

Re: Test Results for AMD Zen 5

#36

Post by adgjlsfhk1 »

KetoManx64 wrote: post #26
heraldgeezer wrote: post #24

Earlier quoted context omitted.

Windows laptops? Desktops for gaming? AMD makes the best gaming CPUs with the X3D series.

What about actually doing something useful to bring prosuctive?

Zen5 is a beat for compilation workloads

Re: Test Results for AMD Zen 5

#37

Post by reitzensteinm »

ashvardanian wrote: post #5

> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…

This is a misreading of their website. On the left, they compare the EPYC 9965 (launched 10/10/24) with the Xeon Platinum 8280 (launched Q2 '19) and make a TCO argument for replacing outdated Intel servers with AMD.

On the right, they compare the EPYC 9965 (launched 10/10/24) with the Xeon Platinum 8592+ (launched Q4 23), a like for like comparison against Intel's competition at launch.

The argument is essentially in two pieces - "If you're upgrading, you should pick AMD. If you're not upgrading, you should be."

Re: Test Results for AMD Zen 5

#38

Post by makeitdouble »

varispeed wrote: post #18

Is it better than M4? If a laptop will need to be plugged in to deliver full performance, whilst blasting fans at full throttle, what is the point? (apart from server / workstation use, where you don't like MacOS or need different OS)

Nowadays laptops are majorly used as desktop hybrids.

Getting near desktop performance when plugged but portability and lower consumption when unplugged is a pretty good tradeoff.

Re: Test Results for AMD Zen 5

#39

Post by ryao »

ryao wrote: post #21
ashvardanian wrote: post #5

> All vector units have full 512 bits capabilities except for memory writes. A 512-bit vector write instruction is executed as two 256-bit writes. That sounds like a weird design choice. Curious if this will affect memcpy-heavy workloads. Writes aside, Zen5 is taking much longer to roll out than I thought, and some of AMD's positioning is (almost expectedly) misleading, especially around AI. AMD's website claims Zen5…

AMD CPUs tend to have more memory bandwidth than Intel CPUs and inference is CPU bound, so their claim seems accurate to me. Whether the core does a 512-bit write in 1 cycle or 2 because it is two 256-bit writes is immaterial. Memory bandwidth is bottlenecked by 64GB/sec per CCX. You need to use cores from multiple CCXs to get full bandwidth. That said, the EYPC 9175F has 614.4GB/sec memory bandwidth and should be ab…

> inference is CPU bound

This was a typo. It should have been “inference is memory bandwidth bound”.

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