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Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

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Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#31

Post by jcranmer »

guywithahat wrote: post #26

As someone who knows almost nothing about CPU architecture, I've always wondered if there could be a new instruction set, better suited to today's needs. I realize it would require a monumental software effort but most of these instruction sets are decades old. RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

> RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

RISC-V is the fifth version of a series of academic chip designs at Berkeley (hence it's name).

In terms of design philosophy, it's probably closest to MIPS of the major architectures; I'll point out that some of its early whitepapers are explicitly calling out ARM and x86 as the kind of architectural weirdos to avoid emulating.

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#32

Post by ksec »

guywithahat wrote: post #26

As someone who knows almost nothing about CPU architecture, I've always wondered if there could be a new instruction set, better suited to today's needs. I realize it would require a monumental software effort but most of these instruction sets are decades old. RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

>I've always wondered if there could be a new instruction set, better suited to today's needs.

AArach64 is pretty much a completely new ISA built from ground up.

https://www.realworldtech.com/arm64/5/

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#33

Post by dehrmann »

guywithahat wrote: post #26

As someone who knows almost nothing about CPU architecture, I've always wondered if there could be a new instruction set, better suited to today's needs. I realize it would require a monumental software effort but most of these instruction sets are decades old. RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

I'm far from an expert here, but these days, it's better to view the instruction set as a frontend to the actual implementation. You can see this with Intel's E/P cores; the instructions are the same, but the chips are optimized differently.

There actually have been changes for "today's needs," and they're usually things like AES acceleration. ARM tried to run Java natively with Jazelle, but it's still best to think of it as a frontend, and the fact that Android is mostly Java and ARM, but this feature got dropped says a lot.

The fact that there haven't been that many changes shows they got the fundamental operations and architecture styles right. What's lacking today is where GPUs step in: massively wide SIMD.

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#34

Post by dehrmann »

jcranmer wrote: post #31
guywithahat wrote: post #26

As someone who knows almost nothing about CPU architecture, I've always wondered if there could be a new instruction set, better suited to today's needs. I realize it would require a monumental software effort but most of these instruction sets are decades old. RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

> RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say) RISC-V is the fifth version of a series of academic chip designs at Berkeley (hence it's name). In terms of design philosophy, it's probably closest to MIPS of the major architectures; I'll point out that some of its early whitepapers are explicitly calling out AR…

> I'll point out that some of its early whitepapers are explicitly calling out ARM and x86 as the kind of architectural weirdos to avoid emulating.

Says every new system without legacy concerns.

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#35

Post by dehrmann »

ItCouldBeWorse wrote: post #30
guywithahat wrote: post #26

As someone who knows almost nothing about CPU architecture, I've always wondered if there could be a new instruction set, better suited to today's needs. I realize it would require a monumental software effort but most of these instruction sets are decades old. RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

I think the ideal would be something like a Xilinx offering, tailoring the CPU- regarding cache, parallelism and in hardware execution of hotloop components, depending on the task. Your CPU changes with every app, tab and program you open. Changing from one core, to n-core plus AI-GPU and back. This idea, that you have to write it all in stone, always seemed wild to me.

I'm fuzzy on how FPGAs actually work, but they're heavier weight than you think, so I don't think you'd necessarily get the wins you're imagining.

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#36

Post by guywithahat »

jcranmer wrote: post #31
guywithahat wrote: post #26

As someone who knows almost nothing about CPU architecture, I've always wondered if there could be a new instruction set, better suited to today's needs. I realize it would require a monumental software effort but most of these instruction sets are decades old. RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say)

> RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say) RISC-V is the fifth version of a series of academic chip designs at Berkeley (hence it's name). In terms of design philosophy, it's probably closest to MIPS of the major architectures; I'll point out that some of its early whitepapers are explicitly calling out AR…

Theoretically wouldn't MIPS be worse, since it was designed to help students understand CPU architectures (and not to be performant)?

Also I don't meet to come off confrontational, I genuinely don't know

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#37

Post by Arnavion »

Asraelite wrote: post #17
AlotOfReading wrote: post #7

Earlier quoted context omitted.

A GPU is a very different beast that relies much more heavily on having a gigantic team of software developers supporting it. A CPU is (comparatively) straightforward. You fab and validate a world class design, make sure compiler support is good enough, upstream some drivers and kernel support, and make sure the standard documentation/debugging/optimization tools are all functional. This is incredibly difficult, but…

> make sure compiler support is good enough Do compilers optimize for specific RISC-V CPUs, not just profiles/extensions? Same for drivers and kernel support. My understanding was that if it's RISC-V compliant, no extra work is needed for existing software to run on it.

You want to optimize for specific chips because different chips have different capabilities that are not captured by just what extensions they support.

A simple example is that the CPU might support running two specific instructions better if they were adjacent than if they were separated by other instructions ( https://en.wikichip.org/wiki/macro-operation_fusion ). So the optimizer can try to put those instructions next to each other. LLVM has target features for this, like "lui-addi-fusion" for CPUs that will fuse a `lui; addi` sequence into a single immediate load.

A more complex example is keeping track of the CPU's internal state. The optimizer models the state of the CPU's functional units (integer, address generation, etc) so that it has an idea of which units will be in use at what time. If the optimizer has to allocate multiple instructions that will use some combination of those units, it can try to lay them out in an order that will minimize stalling on busy units while leaving other units unused.

That information also tells the optimizer about the latency of each instruction, so when it has a choice between multiple ways to compute the same operation it can choose the one that works better on this CPU.

See also: https://myhsu.xyz/llvm-sched-model-1/ https://myhsu.xyz/llvm-sched-model-1.5/

If you don't do this your code will still run on your CPU. It just won't necessarily be as optimal as it could be.

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#38

Post by BitwiseFool »

guywithahat wrote: post #36
jcranmer wrote: post #31

Earlier quoted context omitted.

> RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say) RISC-V is the fifth version of a series of academic chip designs at Berkeley (hence it's name). In terms of design philosophy, it's probably closest to MIPS of the major architectures; I'll point out that some of its early whitepapers are explicitly calling out AR…

Theoretically wouldn't MIPS be worse, since it was designed to help students understand CPU architectures (and not to be performant)? Also I don't meet to come off confrontational, I genuinely don't know

MIPS was a genuine attempt at creating a new commercially viable architecture. Some of the design goals of MIPS made it conducive towards teaching, namely its relative simplicity and lack of legacy cruft. It was never intended to be an academic only ISA. Although I'm certain the owners hoped that learning MIPS in college would lead to wider industry adoption. That did not happen.

Interestingly, I recently completed a masters-level computer architecture course and we used MIPS. However, starting next semester the class will use RISC-V instead.

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#39

Post by trollbridge »

jasoneckert wrote: post #6
ahartmetz wrote: post #5

I don't know, RISC-V doesn't seem to be very disruptive at this point? And what's the deal with specialized chips that the article mentions? Today, the "biggest, baddest" CPUs - or at least CPU cores - are the general-purpose (PC and, somehow, Apple mobile / tablet) ones. The opposite of specialized. Are they going to make one with 16384 cores for AI / graphics or are they going to make one with 8 / 16 / 32 cores tha…

Most of the work that goes into chip design isn't related to the ISA per se. So, it's entirely plausible that some talented chip engineers could design something that implements RISC-V in a way that is quite powerful, much like how Apple did with ARM. The biggest roadblock would be lack of support on the software side.

Doesn't RISC-V have a fairly reasonable ecosystem by now?

Re: Top researchers leave Intel to build startup with 'the biggest, baddest CPU'

#40

Post by jcranmer »

guywithahat wrote: post #36
jcranmer wrote: post #31

Earlier quoted context omitted.

> RISC-V is newer but my understanding is it's still based around ARM, just without royalties (and thus isn't bringing many new ideas to the table per say) RISC-V is the fifth version of a series of academic chip designs at Berkeley (hence it's name). In terms of design philosophy, it's probably closest to MIPS of the major architectures; I'll point out that some of its early whitepapers are explicitly calling out AR…

Theoretically wouldn't MIPS be worse, since it was designed to help students understand CPU architectures (and not to be performant)? Also I don't meet to come off confrontational, I genuinely don't know

The reason why I say RISC-V is probably most influenced by MIPS is because RISC-V places a rather heavy emphasis on being a "pure" RISC design. (Also, RISC-V was designed by a university team, not industry!) Some of the core criticisms of the RISC-V ISA is on it carrying on some of these trends even when experience has suggested that doing otherwise would be better (e.g., RISC-V uses load-linked/store-conditional instead of compare-and-swap).

Given that the core motivation of RISC was to be a maximally performant design for architectures, the authors of RISC-V would disagree with you that their approach is compromising performance.

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