Earlier quoted context omitted.
PCIe is extremely scalable, from Gen1 to Gen5. There is no reason that you couldn't extend one of the GenX specs down to Gen0 speeds. We are already drowning in transistors, I am not convinced by your area argument, esp in the face of shrinking nodes, we have more area than we know what to do with. https://eps.ieee.org/images/files/TC_article_Universal_Chipl... https://www.hpcwire.com/2022/05/11/intel-says-ucie-to-ou…
Yeah uh if you think microcontrollers are on 3nm... No. Most microcontrollers are on 28-40 if not larger. Lower gate widths can sometimes increase logic density and sometimes fmax but they dramatically increase static power, yields, and by extension cost (along with the other factors as outlined by your ieee source). This gross look shows what I believe are some PCIe block die areas. https://substackcdn.com/image/fet…
Please don't put words in my mouth.
I see what you are saying, but you have to put my whole comment together. I am not saying that 8 bit MCUs are going to get GB/s capable PCIe.
Look at things like https://www.efinixinc.com/products-titanium.html with PCIe Gen4 on a 40nm SMIC process. Or more apt, the https://www.wch-ic.com/products/CH384.html PCIe to printer port bridge.
Arguing that I think an Atmega328p should be running PCIe is a ridiculous straw man.