My dad worked on that processor, among others. I see his KF initials in that die photo! :)
Examining the silicon dies of the Intel 386 processor
31–40 of 64 posts
Re: Examining the silicon dies of the Intel 386 processor
#32Re: Examining the silicon dies of the Intel 386 processor
#33Earlier quoted context omitted.
Love the post! Some DOI and Bitsavers links are broken (linking to righto.com or 404s). Also, where can I find "Automatic Place and Route Used on the 80386"? DDG only contains one result: this post.
There was some discussion of the automatic placement in this panel interview. If I remember correctly, the software that performed the placement was written by a graduate student who debugged it from a terminal at his dormitory. It was one of many project decisions on the i386 that management would have absolutely stopped had they been made aware. https://www.computerhistory.org/collections/catalog/10270201... "386 i…
Here are a few:
- > 26 bit address space
- multiplication in hardware
- more complex instructions
- backwards compatibility with the 80286
- on-chip MMU
- support for a FPU
> that justify an order of magnitude?
I wouldn’t know. Backwards compatibility certainly is high on the list because, when it was released, many users had fairly high investments in commercial software.
Re: Examining the silicon dies of the Intel 386 processor
#34Re: Examining the silicon dies of the Intel 386 processor
#35Earlier quoted context omitted.
There was some discussion of the automatic placement in this panel interview. If I remember correctly, the software that performed the placement was written by a graduate student who debugged it from a terminal at his dormitory. It was one of many project decisions on the i386 that management would have absolutely stopped had they been made aware. https://www.computerhistory.org/collections/catalog/10270201... "386 i…
> Did the i386 really have additional features Here are a few: - > 26 bit address space - multiplication in hardware - more complex instructions - backwards compatibility with the 80286 - on-chip MMU - support for a FPU > that justify an order of magnitude? I wouldn’t know. Backwards compatibility certainly is high on the list because, when it was released, many users had fairly high investments in commercial softwar…
Of course, SSE/NEON was decades in the future.
As we note, Intel did not value backwards compatibility at the outset of the i386.
Perhaps an Acorn acquisition and the sudden ownership of a low-power CPU that they could make for peanuts might have also had a profound impact.
It would have been interesting to see Intel making BBC Micros.
Re: Examining the silicon dies of the Intel 386 processor
#36Author here. I've been looking at the 386 if anyone has questions. This post was inspired by userbinator's discussion on HN a couple of weeks ago about how many transistors there are in the 386.
Total amateur here: does a 386 have “cleverness” or optimizations or does it just quite literally chug through a stream of instructions, adjusting registers and memory? I guess by this I am thinking about how newer processors do all kinds of stuff at the microcode level that mean you cannot anticipate precisely what instructions are being executed in what order.
And many have.
"To provide this rich set of instructions, CPUs used microcode to decode the user-visible instruction into a series of internal operations. This microcode represented perhaps 1⁄4 to 1⁄3 of the transistors of the overall design. If... the majority of these opcodes would never be used in practice, then this significant resource was being wasted."
Re: Examining the silicon dies of the Intel 386 processor
#37Earlier quoted context omitted.
But then the 486 DX has a floating-point unit, while the 486 SX does not. So Intel just went with DX is better than SX.
There were rumours that the DX and SX chips were exactly the same: Intel zapped the FPU on the SX to disable it. Apparently it cost more to make, but sold for less.
After the exchange of MMX and 3d-NOW, it was AMD that adopted Intel SSE into amd64.
Re: Examining the silicon dies of the Intel 386 processor
#38My dad worked on that processor, among others. I see his KF initials in that die photo! :)
How were those processors made in a day-to-day basis? What did a typical Intel workspace look like back in the day?
Re: Examining the silicon dies of the Intel 386 processor
#39Author here. I've been looking at the 386 if anyone has questions. This post was inspired by userbinator's discussion on HN a couple of weeks ago about how many transistors there are in the 386.
> ..."tapeout", when the chip data is sent on magnetic tape to the mask fabrication company.
That's roughly true in a temporal sense, but it's not where the term "tapeout" comes from. They could have shipped the data on a Winchester disk, and the event would still be called tapeout.
In the earlier days of printed circuit board (PCB) manufacturing, you would literally "tape out" your circuit manually with black tape on a white board, typically in an enlarged form.
"Tapeout" came to mean the point in time when you finished taping out your circuit and it was ready to be sent to be photographed and reduced and boards manufactured from the layout.
There wasn't even any "data" involved here, magnetic or otherwise. Just a physical art board with tape on it.
Wikipedia has a pretty good article on this:
https://en.wikipedia.org/wiki/Tape-out
And for the young'uns who are wondering "what the heck is a Winchester disk?"
https://www.pcmag.com/encyclopedia/term/winchester-disk
I taped out my first printed circuit board as a third-grader sometime around 1960 and shared the story here:
Re: Examining the silicon dies of the Intel 386 processor
#40Author here. I've been looking at the 386 if anyone has questions. This post was inspired by userbinator's discussion on HN a couple of weeks ago about how many transistors there are in the 386.
The SL die photo seems to really show the differences in density that careful layout can produce; one wouldn't think that bus/memory controllers are of the same complexity as the CPU itself, but due to being entirely standard cells, they are almost the same size as the CPU.