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How a CPU works: Bare metal C on my RISC-V toy CPU

florian.noeding.com

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Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#31

Post by codepoet »

bogomipz wrote: post #28
codepoet wrote: post #24

Earlier quoted context omitted.

Thank you! I'll think about sharing the code. Large code parts - while working - did not pass my quality bar, since I did not have enough time to clean and refactor while learning. But maybe that's fine. Hmm.

>"But maybe that's fine." Oh I think it's more than fine :) Your goal wasn't to write a C++ or Python app it's was to create almost everything from first principles. I also don't think anyone would doubt your abilities after reading this post. You could link to the article in the repo. I think it's speaks for itself. My first thought when I read the article was "Wow, this is great." I've read it twice now. Thank you…

You are right :)

Here's the repo: https://github.com/fnoeding/fpga-experiments

I'll update the post with it too.

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#32

Post by codepoet »

HappyJoy wrote: post #6
codepoet wrote: post #2

I always wanted to understand how a CPU works, how it transitions from one instruction to the next and makes a computer work. So I thought: let's implement one and run a C program on it.

Check out some videos by Ben Eater on Youtube

yes, these are great!

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#33

Post by codepoet »

carry_bit wrote: post #5

Nice that you support multi-cycle memory instead of essentially using a big register file like https://nandgame.com/ uses. I recently came across https://makerchip.com/ , and the TL-Verilog language it supports looks useful for when you want to make a pipelined design later.

The idea with multi-cycle memory was to create a special challenge for myself. Also I thought about using the same technique would be useful if I later on wanted to have mul / div in hardware, which would take a couple of cycles too.

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#34

Post by carry_bit »

codepoet wrote: post #33
carry_bit wrote: post #5

Nice that you support multi-cycle memory instead of essentially using a big register file like https://nandgame.com/ uses. I recently came across https://makerchip.com/ , and the TL-Verilog language it supports looks useful for when you want to make a pipelined design later.

The idea with multi-cycle memory was to create a special challenge for myself. Also I thought about using the same technique would be useful if I later on wanted to have mul / div in hardware, which would take a couple of cycles too.

I'm watching this video about TL-Verilog, and the part starting here shows how powerful it is for that kind of thing: https://youtu.be/hQ6HhOBHKy0?t=2048

In short, you can define generic reusable flow constructs like stall and backpressure pipelines. You can then instantiate them and slot in your logic, and signals will be automatically pulled through the different stages and pipelines as needed. The example at this part of the video shows then how adding something can be a two line change when it would be hundreds of lines if you were working at the RTL level: https://youtu.be/hQ6HhOBHKy0?t=2581

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#35

Post by emoII »

Waterluvian wrote: post #17
PossiblyKyle wrote: post #8

This gets brought up every time the topic shows up but https://www.nand2tetris.org is a course that abstracts how a computer works, and is worth checking out

Is there a version of something like this that’s purely software? Like, emulate gates and keep building bigger pieces until you have a function that’s a CPU. Etc. I guess I’m thinking a bit more lower level than an emulator where you implement an opcode using normal capabilities of your language of choice. I guess TFA is pretty close to this in ways, too.

Worth a mention: https://turingcomplete.game I've played for a few hours, it's well made!

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#36

Post by sylware »

sylware wrote: post #10

Wait we get 64bits risc-v on par with x86_64 on the desktop and arm64 on the mobile... Oh, and what was done, it would be illegal with x86_64 and arm64 as you would have to pay a license in some countries... once you want to make money out of it.

x86_64 and arm64 are not subject to license fees anymore, for instance in the USA?

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#37

Post by bogomipz »

codepoet wrote: post #31
bogomipz wrote: post #28

Earlier quoted context omitted.

>"But maybe that's fine." Oh I think it's more than fine :) Your goal wasn't to write a C++ or Python app it's was to create almost everything from first principles. I also don't think anyone would doubt your abilities after reading this post. You could link to the article in the repo. I think it's speaks for itself. My first thought when I read the article was "Wow, this is great." I've read it twice now. Thank you…

You are right :) Here's the repo: https://github.com/fnoeding/fpga-experiments I'll update the post with it too.

This is great. Cheers!

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#38

Post by MatejKafka »

You might find the QtRVSim simulator interesting:

- WASM version: https://comparch.edu.cvut.cz/qtrvsim/app/

- source & native releases: https://github.com/cvut/qtrvsim

It visualizes the inner workings of a basic RISC-V CPU, you can choose a basic single-cycle CPU, or a full 5-stage pipelined CPU with a hazard unit.

I also recently wrote a 5-stage RISC-V CPU in SystemVerilog, the implementation should be reasonably well-commented:

https://github.com/MatejKafka/risc-v_pipelined_cpu

Re: How a CPU works: Bare metal C on my RISC-V toy CPU

#39

Post by koromak »

LoganDark wrote: post #27
jchw wrote: post #11

Earlier quoted context omitted.

Ben Eater routinely makes me feel ashamed of how awful my breadboard wiring looks. Fantastic videos.

To be fair, all the wires he uses are pre-cut / pre-shaped for the video. The videos are meticulously planned and marvelously executed. Normally hobby projects do not have nearly as much thought put into them.

I've been taking the time to perfectly measure out all the wires on my 8-bit because I don't mind the monotony, its kind of peaceful. But holy hell it takes a long time.

Its like 95% measuring and cutting, 5% thinking, testing and debugging.

Its a bit of a welcome relief from software, which is 95% thinking and 5% typing. A bit of monotony might be good for the brain.

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