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ASML's Secret: A view from inside the global semiconductor giant [video]

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Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#31

Post by doikor »

jve wrote: post #27
doikor wrote: post #12

Earlier quoted context omitted.

Even if they 10x their production you are talking about 200 of the same machine max per year. Nowhere near the numbers where proper industrial automation would make much sense. Also who would be buying these machines if they 10x their production? They go into fabs that costs 10 to 20 billion to build. Let’s say you put 10 of them in each fab. It would still require 150 billion in fab investments every year. There is…

All these numbers remind me how people looked at rocketry pre-SpaceX. "Oh, the most complex, expensive, etc thing in the world" (Rightly so) And then they come in to commoditize the market, make it accessible for lower players by aggressively trying to bring down cost-per-unit via simplicity and process automation. Not saying it could apply to ASML, but I wonder... :)

Lithography equipment isn't some government funded cost+ industry with 0 innovation or competition like what SpaceX had (has?) as its competition. Nobody is using equipment from 70s (Soyuz) or even early 2000s (Atlas or Delta).

It is actually the opposite. Everything is really expensive because you have to be constantly making the newest/greatest thing. A 5 year old lithography machine is pretty much useless for manufacturing high end chips (there is its own market for their output but phones and computers are not it)

Basically if you tried to do the SpaceX way of making a "good enough" rocket (Falcon 9) and use it for a decade+ you would be bankrupt very fast. Nobody wants to pay top dollar for old tech.

edit:

> aggressively trying to bring down cost-per-unit

And what makes you think ASML is not trying to do that? Every cent they save on cost-per-unit increases their profit margin.

Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#32

Post by mensetmanusman »

throwie_wayward wrote: post #10

I absolutely despise the ancient traditional ways they practice: referring to their techniques of 'mystery', secrecy, and occultation of knowledge (which they do in order to construct knowledge as authority and then wield it as power) they've overdone it. by this point they have made it way to fucking difficult for people to truly come to grips with the complexity of modern life mostly becuase in their zealous protec…

What you are describing is tacit knowledge. Something obvious to the workers- but not to outsiders.

Tacit knowledge is hard to pass down in written form because a reader would be overwhelmed by details. It is easier to pass down over video, but video loses information about smell, vibration, static charge, etc. that the human body can feel and learn from.

Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#33

Post by sylware »

hnuser123456 wrote: post #24
sylware wrote: post #17

Well, the video does not show the ppl actually designing the blueprint of the machine and doing the R&D, the real brains... we are showed mostly assembly workers (all above averagely skilled), customer service operators, etc. I was surprised to agree with most of what ASML bosses said, and I would have given exactly the same answer than the assembly operator, namely not providing any timeline... because it is complet…

If I understand correctly, chips down to 14nm were made using ~190nm light, not sure how that worked but if that ratio of 10x+ holds, seems like 1nm fab using 13nm light should be doable with the same techniques, not to mention improved ones?

Idem, if I understand correctly, to go below the light pitch with DUV litographers, multi-patterning had to be used: a huge burden at chip design time and "pressure" on nm-grade alignment equipment (heard about coupled piezo electric motors with xray interferometers?), which is supposed to be from Taiwan.

In other words: photomask madness.

Photomask manufacturing is another critical part of silicium chip manufacturing. It seems EUV photomask are special (no more transparent crystals, but instead reflective "patterned" surfaces?), wonder if they are still using electron/ion beams to engrave patterns.

Wonder where are manufactured EUV photomasks, heard about Japan a lot.

Oh, and I realised that I am really curious on how they keep the EUV mirrors clean from the tin droplets :) Wild guess: EUV mirrors far away, H2 gas reaction, etc?).

Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#34

Post by sylware »

MayeulC wrote: post #30
adrian_b wrote: post #28

Earlier quoted context omitted.

The so-called "5 nm" CMOS processes have minimum pitches around 30 nm. I do not know what minimum pitches are planned for the future so-called "2 nm" CMOS processes, but it is likely that they would not be smaller than 15 to 20 nm. So there will be some time until multiple patterning could be needed again, and by that time there are chances that the transistors will have minimum sizes determined by other causes than…

Gate length is already determined by tunneling current, you can't really go below 20 nm on Si. Width is determined by the current density you want, and can be reduced with better electrostatic control (FDSOI, FinFET, GAA...)

EUV High NA can "draw" 7nm features, with heavy design constraints and alignment equipment, they can sort of go "below", but even with new electrostatic transistor design, they are sort of limited at 20nm for the gate lenght?

Then the litographer does not seem to be the limiting equipment anymore. I guess there is heavy R&D going into electrostatic transistor design and crystals to deal with the gate current below 20nm.

I wonder at which size, silicium doping does not work "enough" anymore.

Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#35

Post by MayeulC »

sylware wrote: post #34
MayeulC wrote: post #30

Earlier quoted context omitted.

Gate length is already determined by tunneling current, you can't really go below 20 nm on Si. Width is determined by the current density you want, and can be reduced with better electrostatic control (FDSOI, FinFET, GAA...)

EUV High NA can "draw" 7nm features, with heavy design constraints and alignment equipment, they can sort of go "below", but even with new electrostatic transistor design, they are sort of limited at 20nm for the gate lenght? Then the litographer does not seem to be the limiting equipment anymore. I guess there is heavy R&D going into electrostatic transistor design and crystals to deal with the gate current below 20…

At some point the electons start tunneling through the channel, regardless of its state... I don't remember my semiconductor theory that well, but possibly unaffected by the height of the potential barrier? In which case better electrostatic control or changing materials does nothing. Hot carriers (high voltages) are more affected, so you can lower voltages to an extent.

You can go below 20 nm, but you get this constant tunneling current, which deteriorates your on/off ratio, and increases power consumption (and TDP). It's doable if you can turn that part of the die off (dark silicon).

Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#36

Post by sylware »

MayeulC wrote: post #35
sylware wrote: post #34

Earlier quoted context omitted.

EUV High NA can "draw" 7nm features, with heavy design constraints and alignment equipment, they can sort of go "below", but even with new electrostatic transistor design, they are sort of limited at 20nm for the gate lenght? Then the litographer does not seem to be the limiting equipment anymore. I guess there is heavy R&D going into electrostatic transistor design and crystals to deal with the gate current below 20…

At some point the electons start tunneling through the channel, regardless of its state... I don't remember my semiconductor theory that well, but possibly unaffected by the height of the potential barrier? In which case better electrostatic control or changing materials does nothing. Hot carriers (high voltages) are more affected, so you can lower voltages to an extent. You can go below 20 nm, but you get this const…

Alright, then if they manage to handle properly this tunneling current in order to get clean on/off, they still will be able to shrink the current transistor feature size... which is actually huge if we don't think about the marketing "Xnm lie", unless another limiting factor hits.

In the silicon crystal lattice, without considering "doping", the atomic valence lenght is 2.35 angstrom or 0.254 nm, and unit lenght 5.44 angstrom or 0.544 nm.

So a feature of 7nm is hardly 14 silicon crystal lattice units. With doping, I wonder if it will be ever required to have a better pitch to have something to work with silicon, unless near "atomic perfect" doping in near "atomic perfect" silicon crystals can still be used for on/off gates.

It makes me pessimistic on the amount of remaining transistor shrink steps. "2nm" maybe "1nm" then you would need to assemble atom per atom perfect lattices frozen in time.

Re: ASML's Secret: A view from inside the global semiconductor giant [video]

#37

Post by bradknowles »

doikor wrote: post #31
jve wrote: post #27

Earlier quoted context omitted.

All these numbers remind me how people looked at rocketry pre-SpaceX. "Oh, the most complex, expensive, etc thing in the world" (Rightly so) And then they come in to commoditize the market, make it accessible for lower players by aggressively trying to bring down cost-per-unit via simplicity and process automation. Not saying it could apply to ASML, but I wonder... :)

Lithography equipment isn't some government funded cost+ industry with 0 innovation or competition like what SpaceX had (has?) as its competition. Nobody is using equipment from 70s (Soyuz) or even early 2000s (Atlas or Delta). It is actually the opposite. Everything is really expensive because you have to be constantly making the newest/greatest thing. A 5 year old lithography machine is pretty much useless for manu…

I worked at ASML for several months in the early 2000s. One of the most surprising things to me was the very long tail they had for old equipment in the field that was still being actively used, and therefore had to be actively supported. Like, stuff that was ten or even twenty years old. I seriously doubt that this situation has materially changed.
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