Earlier quoted context omitted.
How is that a relevant comment in a discussion about ASIC design? I hope you don't have the idea that chip routing is done manually.
IIRC, Place & Route is a known NP complete problem. In this regard, autorouters (whether IC or PCB) can benefit from "better" heuristics -- i.e. it's an optimization problem where AI can help.
Nvidia R&D chief on how AI is improving chip design
31–40 of 81 posts
Re: Nvidia R&D chief on how AI is improving chip design
#32Earlier quoted context omitted.
How is that a relevant comment in a discussion about ASIC design? I hope you don't have the idea that chip routing is done manually.
IIRC, Place & Route is a known NP complete problem. In this regard, autorouters (whether IC or PCB) can benefit from "better" heuristics -- i.e. it's an optimization problem where AI can help.
On a basketball court create a pile of metal plates with bar codes and hooks, each one represents a gate, robot uses rubber bands of sizes vaguely representing timing budget from synthesis to hook the gates together. Robot picks up the whole thing using rubber bands representing the external ports and gives the whole thing a few shakes. Puts it all back down, goes over each metal plate and reads the bar code and resting position - that's your initial routing guess - anneal from there
Re: Nvidia R&D chief on how AI is improving chip design
#33What is extremely telling is what is missing ... Design Rule Checking (DRC) and Layout Vs Schematic (LVS). These require: 1) Longer bit length arithmetic 32-bit float simply isn't enough. 64-bit float is close, but limited. You really want 128-bit integer. And nVidia isn't delivering that. 2) Real algorithmic improvements We're still stuck with computational geometry algorithms that don't parallelize. It would be awf…
Back-of-the-napkin maths is that a chip that is 3cm on each side -- which is huge -- can be subdivided into 0.007 nanometre increments using 32 bit integers. That's 1/7th of the diameter of a hydrogen atom!
The resolution with 64-bit floats (let alone integers) would be absurd, roughly a million times finer-grained still. That's probably enough to simulate individual electrons zipping around in their orbitals with acceptable precision.
Even if the simulation codes did something silly like simply assigning 1.0 = 1cm, a 64-bit float still allows resolutions of something like a billionth of a nanometre...
Re: Nvidia R&D chief on how AI is improving chip design
#34Re: Nvidia R&D chief on how AI is improving chip design
#35What is extremely telling is what is missing ... Design Rule Checking (DRC) and Layout Vs Schematic (LVS). These require: 1) Longer bit length arithmetic 32-bit float simply isn't enough. 64-bit float is close, but limited. You really want 128-bit integer. And nVidia isn't delivering that. 2) Real algorithmic improvements We're still stuck with computational geometry algorithms that don't parallelize. It would be awf…
Can you explain why such large numbers are required? Back-of-the-napkin maths is that a chip that is 3cm on each side -- which is huge -- can be subdivided into 0.007 nanometre increments using 32 bit integers. That's 1/7th of the diameter of a hydrogen atom! The resolution with 64-bit floats (let alone integers) would be absurd, roughly a million times finer-grained still. That's probably enough to simulate individu…
Careful there! Floating point numbers do not form a proper field, not even a semi-group. Due to the uneven distribution of elements, the field axioms don't hold (e.g. both commutativity and distributivity can be violated) and great care has to be taken to assure the numeric stability of computations.
Re: Nvidia R&D chief on how AI is improving chip design
#36It's a shame to see so many people dismissing this work as marketing. I see lots of clever people working hard on really novel and interesting stuff, and I really do think that ML has real potential to customize a design much more "deeply" than traditional automation tools.
Re: Nvidia R&D chief on how AI is improving chip design
#37Re: Nvidia R&D chief on how AI is improving chip design
#38Earlier quoted context omitted.
IIRC, Place & Route is a known NP complete problem. In this regard, autorouters (whether IC or PCB) can benefit from "better" heuristics -- i.e. it's an optimization problem where AI can help.
PCB routing is generally considered a much harder problem. There are a bunch of reasons that add up, but one of them is almost certainly that a PCB is supposed to look good too. The routing on an IC is total chaos (which actually reduces crosstalk issues), but nobody will ever notice.
PCBs "look good" because of different production contraints (and I guess because you're mostly connecting tight-timed busses together)
In ICs you're doing the above but also pulling signals from 10 different places together.
Re: Nvidia R&D chief on how AI is improving chip design
#39Earlier quoted context omitted.
> but it's also extremely NVidia that they're doing it all on their own. Having a lead in chip design is their literal bread and butter. I think it's extremely "publicly traded company" more than "NVidia". Do you have an example of a company releasing an open source version of their secret sauce (foundation of their profits)?
> Having a lead in chip design is their literal bread and butter Sounds tasty, I'll have to take a trip to the nvidia cafe some time =)
Re: Nvidia R&D chief on how AI is improving chip design
#40I work on this team! (Specifically: applied deep learning research, chip design). It's a shame to see so many people dismissing this work as marketing. I see lots of clever people working hard on really novel and interesting stuff, and I really do think that ML has real potential to customize a design much more "deeply" than traditional automation tools.