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Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

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Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#31

Post by test_epsilon »

KirillPanov wrote: post #22

> Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout In other words, this chip isn't even remotely open-source. What they sent to the foundry isn't the "ghost cells" (which don't have transistors in them and therefore don't work). This fails the most basic requirements of being open source.

What is the problem if they could be translated to a working chip? A C program contains no instructions the machine can use and yet you can compile an open source program with a closed source compiler.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#32

Post by nickik »

cjsplat wrote: post #16

For SW type people ... GCC's impact was possible because it was (with GAS - the assembler) 100% feasible to have an open source toolchain. Yes more software was necessary for a complete system (linker, libc, etc), but GCC made it possible to build from the ground floor up. Also, yes, the initial GCC was worse than any proprietary decent tool chain at the time, but it got better and better because each improvement bui…

Google has done a lot of effort in that direction. The first ever chips have already been produced that are fully open source from the tools used to make to the complete tool chain need to manufacture them.

There is a huge amount of great stuff going on this this area.

Tim Ansell - Skywater PDK: Fully open source manufacturable PDK for a 130nm process

https://www.youtube.com/watch?v=EczW2IWdnOM

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#33

Post by lkcl »

nickik wrote: post #32
cjsplat wrote: post #16

For SW type people ... GCC's impact was possible because it was (with GAS - the assembler) 100% feasible to have an open source toolchain. Yes more software was necessary for a complete system (linker, libc, etc), but GCC made it possible to build from the ground floor up. Also, yes, the initial GCC was worse than any proprietary decent tool chain at the time, but it got better and better because each improvement bui…

Google has done a lot of effort in that direction. The first ever chips have already been produced that are fully open source from the tools used to make to the complete tool chain need to manufacture them. There is a huge amount of great stuff going on this this area. Tim Ansell - Skywater PDK: Fully open source manufacturable PDK for a 130nm process https://www.youtube.com/watch?v=EczW2IWdnOM

interestingly, Libre-SOC and NLnet's funding pre-dates the google-sponsored Skywater 130nm process. also, because it's funded by NLnet we're not dependent on google, don't have to pass "conditions", and in particular were not forced to use OpenLane and were not limited to 48 pins controlled by a "Management Engine".

Staf actually developed actual IOpad Cells (from scratch), actual Standard Cells and a 4k SRAM block: we did not use the NDA'd TSMC Cell Libraries, here.

if we had used Skywater 130nm we would have been forced to ditch LIP6.fr (i cannot express enough how hard Jean-Paul Chaput has worked on coriolis2 for the past 18 months), we would not have been able to test the IOpads that Staf developed... yeah.

bottom line is we used a complete independent VLSI toolchain - fully automated - that has nothing to do with the USA or DARPA Military funding - and was developed with European expertise.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#35

Post by lkcl »

throwawaysea wrote: post #21
dragontamer wrote: post #9

A fully open source chip, from Verilog to Fabrication is cool! It may be 180nm (1999-era technology), but that's still hugely important. The world of semiconductor design is incredibly closed source and secretive.

What about the tools and processes to manufacture this? Are those open source or broadly available? For instance, is it possible to have a small scale "community" fab for 1999-era chip technology?

yes, Chips4Makers http://chips4makers.io will help anyone who wants to do a 360nm ASIC, the costs are ridiculously cheap. like... EUR 1750 for 20 MPW samples, something mad, who would have ever thought it.

Staf will also "protect" you from the Foundry NDAs. you develop with a "symbolic" version of the Cell Library, he runs the "Real" one and sends it to IMEC on your behalf. here's Staf's "symbolic" Cell Library, it's based on FreePDK45 https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/releases

Coriolis2 - http://coriolis.lip6.fr/ - is entirely Libre-Licensed. it's fully automated, you don't have to do any "hand-editing", it has unit tests (so you have demos you can look at and also check you installed everything right). we have some automated setup scripts for it if you're interested: https://git.libre-soc.org/?p=dev-env-setup.git;a=blob;f=cori...

LIP6 have a Silicon-proven ENTIRELY Libre Cell Library called nsxlib, if you really want to go that route. it's Silicon-proven in 360nm and 180nm.

Also, LIP6 have a relationship with a small town in Japan, they have 2 micron fab which is used for "training" of employees of the town. submission for that is entirely free. i know this exists but have not used it, and don't know more details, but i can probably put you in touch with Sorbonne University if you're serious.

and if you really really want to do "at home" stuff, Libre-Silicon is developing a 2in wafer fab, using Ultra-Violet DLPs and high-accuracy stepper motors, that you'll be able to buy and operate from your garage or lab. think "3D printing", i think they're aiming for 2000 nm or something (20 micron)? really big, but proves the concept.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#36

Post by lkcl »

addaon wrote: post #10
cdcarter wrote: post #5

Earlier quoted context omitted.

Who is this important for? Is there a lot of software still being developed for POWER? It seems niche to me, but maybe I'm the one in a niche.

The POWER/PowerPC ISA is still widely used in safety-critical avionics, where a mature tool-chain exists for supporting DO-178 objectives. In my opinion, an area of interest going forward into the next decade of more safety-critical software written by smaller and smaller orgs (e.g. eVTOL companies, sensor companies, etc) is continuing to push forward which objectives can be accomplished by formal means instead of pr…

> The POWER/PowerPC ISA is still widely used in safety-critical avionics

and in the Mars Rover, which is a radiation-hardened 133mhz 32-bit Power ISA system.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#37

Post by lkcl »

KirillPanov wrote: post #22

> Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout In other words, this chip isn't even remotely open-source. What they sent to the foundry isn't the "ghost cells" (which don't have transistors in them and therefore don't work). This fails the most basic requirements of being open source.

HDL source code: https://git.libre-soc.org/?p=soc.git;a=summary

Coriolis2 source code: http://coriolis.lip6.fr/

Chips4Makers FlexLib Cell Library based on FreePDK45: https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/releases

Automated Layout scripts for generation of GDS-II Files: https://git.libre-soc.org/?p=soclayout.git;a=summary

please do try to get your facts right and not mislead people by making false claims, eh?

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#38

Post by lkcl »

test_epsilon wrote: post #31
KirillPanov wrote: post #22

> Symbolic (ghost) versions of FlexLib allowed Libre-SOC developers to not have to sign a Foundry NDA during the development of the ASIC Layout In other words, this chip isn't even remotely open-source. What they sent to the foundry isn't the "ghost cells" (which don't have transistors in them and therefore don't work). This fails the most basic requirements of being open source.

What is the problem if they could be translated to a working chip? A C program contains no instructions the machine can use and yet you can compile an open source program with a closed source compiler.

we used an entirely Libre-licensed VLSI "compiler", which takes HDL as input and spits out fully-completed GDS-II Files.

the problem with this particular irate individual is that he's assumed that because TSMC's DRC rules are only accessible under NDA that automatically absof*** everything was also "fake open source".

idiot.

sigh.

clearly didn't read the article.

whilst both Staf Verhaegen and LIP6.fr signed the TSMC Foundry NDA, we in the Libre-SOC team did not. we therefore worked entirely in the Libre world, honoured our committment to full transparency, whilst Staf and Jean-Paul and the rest of the team from LIP6 worked extremely hard "in parallel".

the ASIC can therefore be compiled with three different Cell Libraries:

* LIP6.fr's 180nm "nsxlib" - this is a silicon-proven 180nm Cell Library * Staf's FreePDK45 "symbolic" cell library using FlexLib (as the name says, it uses the Academic FreePDK45 DRC) * the NDA'd TSMC 180nm "real" variant of Staf's FlexLib

i was therefore able to "prepare" work for Jean-Paul, via the parallel track, commit it to the PUBLIC REPOSITORY (the one that's open, that our resident idiot didn't bother to check existed or even ask where it is), which saved Jean-Paul time whilst he focussed on fixing issues in coriolis2.

it was a LOT of work.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#39

Post by gnufx »

Seirdy wrote: post #27
cdcarter wrote: post #5

Earlier quoted context omitted.

Who is this important for? Is there a lot of software still being developed for POWER? It seems niche to me, but maybe I'm the one in a niche.

Many hyperscalar server setups use POWER8/POWER9 CPUs. 4 logical processes per core (and 8 with the upcoming 15-core POWER10 configurations) are pretty useful when measuring perf-per-watt. The Talos is currently the only fully libre computer available for high-perf computing, and it uses POWER9 CPUs. If you want a fully free CPU, your choices are either very dated CPUs or POWER. Many distros (inc. Debian, and most so…

Actually, SMT8 P8 and P9 is documented, though it seems rare. Our HPC systems are only SMT4, anyhow.

Yes, you can just install most of at least Debian, Fedora, RHEL, at least, though it needs an "alt" kernel on RHEL7 P9. There are a few things which haven't been ported, mainly due to assembler, I guess. (PRoot and DMTCP are two I know.) Even x86 SIMD intrinsics will largely work, if not necessarily very efficiently.

Re: Libre-SoC 180nm Power ISA v3.0 ASIC Submitted to IMEC MPW

#40

Post by ploxiln »

lkcl wrote: post #33
nickik wrote: post #32

Earlier quoted context omitted.

Google has done a lot of effort in that direction. The first ever chips have already been produced that are fully open source from the tools used to make to the complete tool chain need to manufacture them. There is a huge amount of great stuff going on this this area. Tim Ansell - Skywater PDK: Fully open source manufacturable PDK for a 130nm process https://www.youtube.com/watch?v=EczW2IWdnOM

interestingly, Libre-SOC and NLnet's funding pre-dates the google-sponsored Skywater 130nm process. also, because it's funded by NLnet we're not dependent on google, don't have to pass "conditions", and in particular were not forced to use OpenLane and were not limited to 48 pins controlled by a "Management Engine". Staf actually developed actual IOpad Cells (from scratch), actual Standard Cells and a 4k SRAM block:…

These details are fascinating and non-obvious. Every little tool or part you have to use to work with even 15-year old chip fab processes is under NDA.

It's hard to come up with a good analogy ... it's like you need to write your own serial driver for your new open-source programming language to do any I/O, because you can't call any libraries or OS syscalls because they're all NDA, even on a 15+ year old computer/OS.

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