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Computing Performance on the Horizon

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Re: Computing Performance on the Horizon

#31

Post by hobofan »

thechao wrote: post #26
martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

Aren't "big" 3D circuits unfeasible due to temperature limitations, though?

Re: Computing Performance on the Horizon

#32

Post by nradov »

thechao wrote: post #26
martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

How are we going to cool those 3D chips?

Re: Computing Performance on the Horizon

#33

Post by yjftsjthsd-h »

thechao wrote: post #26
martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

> in 2D layout is NP-hard (complete) without efficient polynomial approximations; in 3D layout is low-order polynomial

Any chance you could explain to a novice why 3D is easier? To my naive intuition, it would have seemed like the more room to maneuver is offset by having more stuff to route.

Re: Computing Performance on the Horizon

#34

Post by a1369209993 »

hobofan wrote: post #31
thechao wrote: post #26

Earlier quoted context omitted.

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

Aren't "big" 3D circuits unfeasible due to temperature limitations, though?

> Aren't "big" 3D circuits unfeasible due to temperature limitations, though?

Less so than you'd think, since (as long as you can keep leakage current under control) heat is only generated when the circuits are active (barring leakage current, when bits are being flipped). So you can have arbitrarily large amounts of increasingly-rarely-used circuitry for various purposes.

The naive-but-easy-to-understand example would be having separate, optimal circuitry for each machine instruction - the total number of gates is O(N*M), but the number of gates activated on each clock cycle (and thus the amount of waste heat generated) is only O(N), so you can keep adding new, perfectly-hardware-accelerated instructions up to the limits of physical space. In practice it's more complicated and less of a nonissue, but it's not "big circuits are useful in proportion to their surface area, not their volume", it's more "big circuits are less useful than their volume alone would suggest". (You do hit physical limits like the Bekenstein bound[0] eventually, but that's far enough out that we mostly don't care yet.)

0: https://en.wikipedia.org/wiki/Bekenstein_bound

Re: Computing Performance on the Horizon

#35

Post by uluyol »

handrous wrote: post #16
martinpw wrote: post #10

Slide 26 is interesting - arguing that cloud providers have an advantage for future CPU design since they can analyze so many real world customer workloads directly. In previous roles I have worked with CPU vendors who have been very keen on getting access to profiling data from our workloads for design optimization, and lamenting the fact that it was hard to get such data and they were often limited to synthetic ben…

An interesting application of a now-familiar pattern: get lots of users, spy on them at massive scale, use those data to dominate some other market in a way that, at most, a single digit count of companies in the world could conceivably compete with (because none but they have anything like the data that you do). See also: everything to do with "AI".

Amazon, Microsoft, and Google have massive applications and systems that they run, some of which they sell as a service. They have plenty of workload data without having to poke around user VMs.

Re: Computing Performance on the Horizon

#36

Post by dragontamer »

zozbot234 wrote: post #29
dragontamer wrote: post #22

Earlier quoted context omitted.

Not quite. DDR4 and DDR5 have 50ns (single socket) to 150ns (dual socket) latency. For a 3GHz processor, that's 150 to 450 cycles. On any latency bound problem, SMT helps. However, what you say is true on bandwidth bound problems. Given the shear number of pointer hopping that happens in typical OOP code these days (or python / JavaScript), I expect SMT to be of big help to typical applications. DDR5 will double band…

Memory bandwidth is just barely trying to keep up with cores, frequencies and IPC amounts. Bandwidth available per core is still going to drop. So newer development workflows that optimize for this bottleneck are going to be very relevant.

Memory bandwidth does improve at least.

Latency hasn't improved for the last 30 years. Tricks like SMT which can help mitigate the latency issue seem like the way forward.

Re: Computing Performance on the Horizon

#37

Post by thechao »

yjftsjthsd-h wrote: post #33
thechao wrote: post #26

Earlier quoted context omitted.

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

> in 2D layout is NP-hard (complete) without efficient polynomial approximations; in 3D layout is low-order polynomial Any chance you could explain to a novice why 3D is easier? To my naive intuition, it would have seemed like the more room to maneuver is offset by having more stuff to route.

Try laying out a square with all the vertices connected in a plane: it’s not possible. You must move one of the wires “up” a layer. Which wire? Great layout minimizes layer transitions while also bunching together related HW blocks. The NP-completeness proof is related to work Knuth’s student (Plass?) did on laying out images in TeX.

Re: Computing Performance on the Horizon

#38

Post by infogulch »

ksec wrote: post #27

>for storage including new uses for 3D Xpoint as a 3D NAND accelerator; 3D XPoint's future is not entirely certain. Intel with their new CEO has remained rather quiet on the subject. Micron are pulling the plug on it and sold the Fab to Texas Instrument. The problem is there isn't a clear path forward with the technology, it make some sense when NAND and DRAM price were high in 2016 - 2019. Once they dropped to a nor…

> Are there really no use-case where 128 Core+ with NUMA offer some advantage?

Are there any use cases where 128+ core single socket wouldn't be preferred to a 128+ core multiple socket design that is burdened by NUMA?

AMD has been showing us that integrating the interconnects into the CPU package directly and letting it handle all the issues is a better design.

Re: Computing Performance on the Horizon

#39

Post by handrous »

uluyol wrote: post #35
handrous wrote: post #16

Earlier quoted context omitted.

An interesting application of a now-familiar pattern: get lots of users, spy on them at massive scale, use those data to dominate some other market in a way that, at most, a single digit count of companies in the world could conceivably compete with (because none but they have anything like the data that you do). See also: everything to do with "AI".

Amazon, Microsoft, and Google have massive applications and systems that they run, some of which they sell as a service. They have plenty of workload data without having to poke around user VMs.

You disagree with slide 26, then?

Re: Computing Performance on the Horizon

#40

Post by thechao »

nradov wrote: post #32
thechao wrote: post #26

Earlier quoted context omitted.

He sort of implies that “just better hardware” will peter out in the 2030s. I think he’s calling it at least 50 years too soon. Here’s why: (1) I think logic designers are still faffing about in term of optimizing their designs; and (2), I think there’s a lot of smart people thinking “incrementally” through what we’d consider paradigm shifts in HW implementation. That is, our fabs will just naturally segue into 3D, s…

How are we going to cool those 3D chips?

The commenter above is correct: just stop toggling HW. We already do this to a great extent; we’re limited in the number of custom implementations because we can’t wire everything together. 3D chips will have a lot more “dark” logic than current chips, but will be orders-of-magnitude more efficient (& thus powerful) due to deep customization.

Also, remember the argument of my timeline is ~50–80 years out from now.

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