Hacker News Board Hacker News, browsed like a classic message board
Live data from Hacker News

SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

tomshardware.com

Post reply on HN
Print view View original

31–40 of 87 posts

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#31

Post by lizknope »

zibzab wrote: post #15
lizknope wrote: post #10

Earlier quoted context omitted.

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

Sounds like OSH Park for silicon... Anyway, I'm still not sure why SiFive is doing this. Seems like a waste of money even as a prototype

The article mentions that is is from the OpenFive division of SiFive. OpenFive used to be Open Silicon and their business model was working with other companies to take their Verilog RTL and do all of the physical design (synthesis to logic gates, place and route of the standard cells, timing analysis, test vector generation) and then work with the foundries to deliver all of the data for manufacturing.

Since Open Silicon is now OpenFive and part of SiFive they literally have all this experience in house and don't need to depend on another company between them and TSMC.

https://en.wikipedia.org/wiki/Open-Silicon

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#32

Post by dragontamer »

zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

Routers / Switches have extremely weird performance characteristics, and I think that's what SiFive is targeting with this chip.

* HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which means your physical RAM-bandwidth needs to be an order of magnitude greater than that)

* Embedded 32-bit design for low-power usage.

* All switches have small, fixed size buffers. Memory capacity is not a problem, its feasible to imagine useful switches and routers (even 10Gbps, 40Gbps, or 100Gbps) that only have hundreds-of-MBs of RAM. As such, 32-bit is sufficient and 64-bit is a waste (You'd rather half your pointer memory requirements with 32-bit pointers rather than go beyond 4GB capacity)

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#33

Post by varispeed »

lizknope wrote: post #10
ohazi wrote: post #3

I know they're separate lines and capacity is sold well in advance and all that, but this chip shortage still baffles me. A startup can tape out a 5 nm chip, but STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year? Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months o…

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

Out of curiosity - what software is being used to design chips? Is there anything within reach of a small company, or something open source?

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#34

Post by rjsw »

dragontamer wrote: post #32
zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

Routers / Switches have extremely weird performance characteristics, and I think that's what SiFive is targeting with this chip. * HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which m…

Routers need quite a bit of memory to handle IPv6.

Switches as an application of this makes sense.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#35

Post by winter_blue »

HBM might be an interesting idea. I would love to see multiple bandwidth levels of memory becoming a norm, with computers a very fast small amount of memory, and a larger set of DRR4 or DRR5. We already have multiple levels of cache, why not having multiple levels of RAM? Operating systems and software would need to accommodate a new reality where NUMA is the norm though. But it’s good that we even have the concept of NUMA, so this is not entirely uncharted/unfamiliar territory.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#36

Post by thechao »

varispeed wrote: post #33
lizknope wrote: post #10

Earlier quoted context omitted.

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

Out of curiosity - what software is being used to design chips? Is there anything within reach of a small company, or something open source?

Front-end is HDLs — (System)Verilog, VHDL, etc. Implementation and formal will be Jasper & its ilk. Backend (physical, etc.) use fab-specific bespoke software from the majors (Cadence, NXP, MG, Synopsis, ...).

The front-end stuff could be done by one person; Verilator is a great example (although it's now "in house" to NXP). Implementation, LEC, etc. are mathematically intimidating -- they're proof engines -- but doable by a small team.

Physical requires inside knowledge of the fabs. The fabs aren't going to let you participate unless you're a major, because it costs them a lot of money, and each additional participant is another potential leak of their critical IP.

The tooling is all "vertical" and starts on the backend. If you can't do backend, you're not a player.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#37

Post by foobiekr »

dragontamer wrote: post #32
zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

Routers / Switches have extremely weird performance characteristics, and I think that's what SiFive is targeting with this chip. * HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which m…

While these are all good points, this really does not appear to be a competitive NPU design on any axis that matters. I don’t know what this chip is for, but a router NPU it is not, nor a switch. Maybe some soho switch or smart NIC, but those have moved on far along the performance spectrum away from the place where this would fit.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#38

Post by jecel »

varispeed wrote: post #33
lizknope wrote: post #10

Earlier quoted context omitted.

I'm in the semiconductor company. I don't really understand your question. Anyone can start a company and tape out a chip even in 5nm. My previous startup did something similar. We used an intermediate company between us and TSMC that specifically works with smaller companies. They (or TSMC) will bundle together 4 to 20 chips into a common mask as a "shuttle" run. Shuttle runs are really only used to get samples for…

Out of curiosity - what software is being used to design chips? Is there anything within reach of a small company, or something open source?

The commercial tools are indeed very expensive but the required data files can be as much of a problem. Normally you have to sign a bunch of NDAs (non disclosure agreements) to get your hands on the design rules and standard cell libraries supplied by the foundries and required to make the tools work.

One effort to organize several previously available open source tools into a practical system is OpenLane, which is based on the DARPA OpenRoad project:

https://woset-workshop.github.io/PDFs/2020/a21.pdf

Recently, Google has financed a project where a foundry has made its data files available without any NDAs:

https://github.com/google/skywater-pdk

The combination has made it possible to have completely open source chip designs.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#39

Post by PragmaticPulp »

ohazi wrote: post #3

I know they're separate lines and capacity is sold well in advance and all that, but this chip shortage still baffles me. A startup can tape out a 5 nm chip, but STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year? Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months o…

> Also car companies are supposedly the culprit, even though their volume is only in the low tens of millions per year, and the dustup is apparently over only six months of capacity? What? I get that the auto industry is a nice reliable long-term source of revenue for chip companies, but fabs should barely be sneezing at that sort of volume.

I agree. I think the blame on automakers has been blown out of proportion. It doesn't make any sense that automakers cancelled orders, then reinstated those orders again with some extra demand, and now the entire chip market is stalled.

It's most likely due to the fact that consumer demand is up everywhere. The pandemic didn't hit the economy nearly as hard as expected, and we piled a lot of stimulus on top of that. Savings rate went up a bit, but much discretionary spending was diverted away from things like dining out and toward buying consumer goods.

> STMicroelectronics can't make any of their 40-130 nm microcontrollers for the next year

They're almost certainly making huge volumes of microcontrollers, but they're all spoken for with orders from the highest bidders.

We won't have inventory sitting on shelves again until fab capacity isn't being 100% occupied by existing orders. Need some surplus before we can get parts at DigiKey.

Re: SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7.2 Gbps HBM3

#40

Post by Fordec »

zozbot234 wrote: post #13

IIRC, 32-bit RISC-V is only intended for deep embedded workloads, with 64-bit for general purpose compute. So a SoC w/ a single 32-bit core would seem to be a less-than-ideal fit for the cutting-edge 5nm process.

With my industry / product management / business strategy hat on, totally agree from SiFive's perspective.

With my early days electronics hat on, the 5nm process adds additional energy performance gains that in conjunction with RISCV in an embedded environment, especially in a battery powered remote operation use case, has me salivating at what could be achieved from a would-be customer perspective.

Post reply on HN