Earlier quoted context omitted.
If SRAM is as ubiquitous throughout chip designs as the article suggests, wouldn't that mean the theoretical density prediction is off?
Time for eDRAM! Ok, this process doesn't support eDRAM. Also, I don't understand the SRAM scaling failure here and I don't know if it would apply to eDRAM too. But it's something to think about given the increasing importance of wire delay.
I think we just have to accept that silicon scaling is slowing down.