31–40 of 84 posts
Ten years ago, in grad school, I co-wrote a video conferencing module in VHDL [0]. I haven't touched HDLs since but here's what I remember very clearly from that project: * It took > 3 minutes to compile our code. * DMA made a huge performance difference once we figured it out. * Realizing that we had to be one with the clock tick took a lot of time. Understanding synchronous based programming (if that's the term) wa…
Ten years ago, in grad school, I co-wrote a video conferencing module in VHDL [0]. I haven't touched HDLs since but here's what I remember very clearly from that project: * It took > 3 minutes to compile our code. * DMA made a huge performance difference once we figured it out. * Realizing that we had to be one with the clock tick took a lot of time. Understanding synchronous based programming (if that's the term) wa…
Your PDF link is a 404.
Small error in the article: 200*10e6 is 2GHz, not 200MHz.
Ha, good eye. corrected to 1e6 :)
The problem of FPGAs is their proprietary nature, and Verilog/VHDL are far from the best languages. Gladly there is a number of open-source projects aiming to close this gap - Yosys[1], SymbiFlow[2], Chisel3[3]/FIRRTL[4]. Some time ago I suggested[5] different open source projects should unite and reuse the common intermediate language, akin to LLVM in many software development and analysis tools. From my point of vi…
I'm surprised that no one has brought up the Lattice IceStick. It's an oversized USB stick with an ice40 FPGA on it and it's the cheapest option I've seen.
The latter requires a USB blaster dongle to program things so the Upduino has the upper hand IMO, especially because it also has very lightweight open source tools.
Earlier quoted context omitted.
Ha, good eye. corrected to 1e6 :)
Nice work. FPGA design appears to be very similar to GPU shader programming. First time I've read anything about FPGA design that connected. Usually FPGA stories get lost in data flow jargon and I learn nothing.
I recently got a TinyFPGA-BX, and have been slowly working through the tutorials. The amusing thing is that, for the actual applications I'm working on, a contemporary microcontroller can actually keep up just fine, and is easier for me to comprehend. Still, one of these days, a use will for an FPGA will crop up for which I'll be glad that I learned.
Great article, I wish the discussions around clocks had gone a bit more into how the tradeoff of pipelining vs longest operation ends up impacting designs. That and SRAM vs DRAM access latencies were the things that really connected the dots from how performance optimization on the software side of things is rooted in physical hardware limitations.