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Evolution of the x86 context switch in Linux (2018)

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Re: Evolution of the x86 context switch in Linux (2018)

#32

Post by berti »

monocasa wrote: post #20
pantalaimon wrote: post #13

Earlier quoted context omitted.

Abbreviating the C Preprocessor as cpp is very confusing imho.

It's a common abbreviation older than C++. You used to even be able to run the c pre processor on arbitrary non-C files by using the cpp command.

You still can.

Re: Evolution of the x86 context switch in Linux (2018)

#33

Post by amluto »

souprock wrote: post #29
bogomipz wrote: post #28

Earlier quoted context omitted.

>"Of course, that turns out to be the fix for meltdown, unless you have the process-context identifiers (PCID) available on Haswell chips and newer." Using TSS based switching is incompatible with PCIDs? Or is it incompatible with separate address spaces for user space and kernel space? PCIDs are process ID tags on cache lines correct?

TSS switching is incompatible with running in 64-bit mode. It is very slow. Doing most of the same actions (reload segment registers and the page table base) in software is also very slow. Prior to the meltdown issue, Linux system calls had avoided most reloads of the segment registers and page table base. PCIDs are incompatible with older hardware. They are modestly slow. I think the PCID state includes the TLB. Tha…

I think you may be a bit confused here. PCID is a feature that lets the kernel avoid a TLB when CR3 is written. With or without PCID, CR3 gets written. The segment registers have nothing whatsoever to do with this on a 64-bit system.

Re: Evolution of the x86 context switch in Linux (2018)

#34

Post by souprock »

amluto wrote: post #33
souprock wrote: post #29

Earlier quoted context omitted.

TSS switching is incompatible with running in 64-bit mode. It is very slow. Doing most of the same actions (reload segment registers and the page table base) in software is also very slow. Prior to the meltdown issue, Linux system calls had avoided most reloads of the segment registers and page table base. PCIDs are incompatible with older hardware. They are modestly slow. I think the PCID state includes the TLB. Tha…

I think you may be a bit confused here. PCID is a feature that lets the kernel avoid a TLB when CR3 is written. With or without PCID, CR3 gets written. The segment registers have nothing whatsoever to do with this on a 64-bit system.

The explanation is a bit awkward because I'm trying to describe numerous situations. (pre-2.2 kernels, post-meldown kernels, in-between kernels, 32-bit builds, 64-bit builds, using PCID hardware, not using PCID hardware...) It looks like 7 of the 12 possibilities are valid, more or less.

Some segment registers are reloaded on a 64-bit system. That includes CS, DS, SS, and GS. The 32-bit systems must additionally reload ES. All segment registers are loaded for Linux 2.0 and older, via hardware task switching.

CR3 does not get written for system calls when running on a normal Linux from version 2.2 until the meltdown workaround hit.

Re: Evolution of the x86 context switch in Linux (2018)

#35

Post by loeg »

monocasa wrote: post #21
loeg wrote: post #12

Earlier quoted context omitted.

In particular, a single statement. I'm sure the link covers it, but: if (foo) MULTI_LINE_MACRO; Breaks without some wrapper like if (1) { A; B; } or do { A; B; } while (0): if (foo) A; B; // oops, unconditional (e.g., "goto fail")

It also gives you a nice scope to keep local variables in, but there are other ways to accomplish that too.

Yeah, that's a good point too.
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