The article seems to say FPGA on a high latency bus can only accelerate workload that are streamed via DMA, and implies that a general purpose accelerator has to be closer to the CPU. Sounds like a coprocessor, like putting an FPGA into the slot where the 8087 used to be. That made me think, why not get even closer? Why not have an FPGA as execution unit? Modern CPUs have multiple ALUs, multiple FPUs, multiple vector…
Project page: https://www.microsoft.com/en-us/research/project/emips/
Research paper: https://www.microsoft.com/en-us/research/wp-content/uploads/...
Back then Moore's Law was still going full steam so there wasn't much interest but, who knows, maybe that will change in a few years.