31–40 of 61 posts
Earlier quoted context omitted.
I was talkin about Ryzen 8core more actually. Those have low clock speed. And are called EPYC.
Got it. For what it's worth I think EPYC is based on the same "Zen" arch as Ryzen.
Not every workload is memory bandwidth bound like his "make -j16" compile. Some workloads need memory latency or fast inter-core (and inter-socket) operations (e.g. RDBMS OLTP), some need CPU throughput (e.g. HPC), some need best possible single thread CPU performance (e.g. some gaming). As he wrote, CPUs are most efficient (compute per Watt) at a specific frequency, and if his CPU mostly waits for RAM, this can be d…
Zen is already light on vector units, and microcodes 256-bit operations. It's certainly possible to build a more lightweight core, but most of that work is reducing the complexity of the out-of-order machinery. The FPU+ALU is under a quarter of each Zen core. https://en.wikichip.org/w/images/c/cb/amd_zen_core_%28annota...
Which mean the CPU is already shipped with the reasonable performance/watt TDP and over-TDP it will give diminish return in performance gain.
However, It would be interesting to see benchmark in much lower TDP than 105Watt and see how far the TDP can go down before big drop in performance.
Earlier quoted context omitted.
Zen is already light on vector units, and microcodes 256-bit operations. It's certainly possible to build a more lightweight core, but most of that work is reducing the complexity of the out-of-order machinery. The FPU+ALU is under a quarter of each Zen core. https://en.wikichip.org/w/images/c/cb/amd_zen_core_%28annota...
Do you have a link about microcoded avx256? I would think it would be way too slow.
https://www.agner.org/optimize/blog/read.php?i=838#838
This is responsible for Ryzen losing to Intel in SIMD heavy benchmarks. The upside is that it avoids the reduced turbo boost Intel does for some 256-bit AVX instructions (and even worse downclocks caused by AVX 512), so for workloads mixing avx and normal instructions it shouldn't do too badly.
Earlier quoted context omitted.
Do you have a link about microcoded avx256? I would think it would be way too slow.
> 256-bit vector instructions (AVX instructions) are split into two micro-ops handling 128 bits each. https://www.agner.org/optimize/blog/read.php?i=838#838 This is responsible for Ryzen losing to Intel in SIMD heavy benchmarks. The upside is that it avoids the reduced turbo boost Intel does for some 256-bit AVX instructions (and even worse downclocks caused by AVX 512), so for workloads mixing avx and normal instruc…
I think the claim that parallel compilation with gcc is memory bandwidth bound is unlikely. gcc is known to be a very pointer-chasy, branch-mispredicty load that is highly sensitive to memory latency - far from a streaming load that is sensitive to raw bandwidth. Still, the conclusion holds: if most of the time is spent waiting for values to come back from memory, a higher core frequency has strongly diminishing retu…
That be much more CPU-bound. Yes - some optimization will do global traversals.
I wonder if javac/clang has the same characteristics as gcc.
Earlier quoted context omitted.
> 256-bit vector instructions (AVX instructions) are split into two micro-ops handling 128 bits each. https://www.agner.org/optimize/blog/read.php?i=838#838 This is responsible for Ryzen losing to Intel in SIMD heavy benchmarks. The upside is that it avoids the reduced turbo boost Intel does for some 256-bit AVX instructions (and even worse downclocks caused by AVX 512), so for workloads mixing avx and normal instruc…
I see, yep - but this is still hardwired stuff happening in instruction decode, as Agner writes, not trapping to microcode sequencing.
I think the claim that parallel compilation with gcc is memory bandwidth bound is unlikely. gcc is known to be a very pointer-chasy, branch-mispredicty load that is highly sensitive to memory latency - far from a streaming load that is sensitive to raw bandwidth. Still, the conclusion holds: if most of the time is spent waiting for values to come back from memory, a higher core frequency has strongly diminishing retu…