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AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

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Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#291

Post by sofixa »

ac29 wrote: post #284
sofixa wrote: post #151

Earlier quoted context omitted.

> AMD has been making SoCs forever. Why does it take a kick in the teeth from Apple for both Intel and AMD suddenly to wake up and give us performance SoCs, 5 years later What do you mean? AMD has been the market leader in performance SoCs for specialised use cases (like consoles) for many years.

There are only two high performance consoles on the market, and AMD happens to make both the chips. I guess you could say they are the "market leader", but that is in part because there are so few consoles out there. Nvidia or Intel could certainly make a console focused SoC at least as performant as AMD.

> Nvidia or Intel could certainly make a console focused SoC at least as performant as AMD.

They certainly cannot, or they would have. Do you think that Sony and Microsoft stay with AMD because they like them or because AMD can deliver what they want?

> There are only two high performance consoles on the market

I'd throw the Steam Deck on that list too. High performance for its size more than high performance in general, but still. It's no coincidence that all the gaming handheld consoles, full blown consoles, and lots of gaming devices in general all use AMD.

Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#292

Post by tempnow987 »

crest wrote: post #248
tempnow987 wrote: post #243

Earlier quoted context omitted.

No question - but these kind of games lead to poor adoption. They made a big todo about how much better than AMD they are with things like AVX512. Then they play these games for market purposes. Then they have stupid clock speed pauses, so when you try it your stuff goes slower. Meanwhile - AMD is putting it on all their chips and it works reasonably there. So I've just found the whole Intel style here kind of annoyi…

Or Intel's repeated failures to roll out a working <14nm processes forced them to cripple even the P-core AVX-512 implementation (one less ALU port compared to Xeon Gold), rip out whatever compatibility feature they wanted to put in the E-cores and Microsoft refused to implement workarounds in Windows (e.g. make AVX-512 opt-in and restrict threads that enabled it to P-cores, reschedule threads faulting on AVX-512 ins…

Fair point - that cycle took FOREVER. I remember when their marketing slides starting doing comparisons between their unreleased future products and current (and sometimes about to be replaced) competitor products.

Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#293

Post by camel-cdr »

dzaima wrote: post #181
camel-cdr wrote: post #45

Earlier quoted context omitted.

AVX512 was never over 2 cycles. In Zen4 it used the 256 wide execution units of avx2 (except for shuffle), but there are more then one 256-bit wide execution units, so you still got your one cycle throughput.

More importantly for the "2 cycles" question, Zen 4 can get one cycle latency for double-pumped 512-bit ops (for the ops where that's reasonable, i.e. basic integer/bitwise arith). Having all 512-bit pipes would still be a massive throughput improvement over Zen 4 (as long as pipe count is less than halved), if that is what Zen 5 actually does; things don't stop at 1 op/cycle. Though a rather important question with…

> Having all 512-bit pipes would still be a massive throughput improvement over Zen 4 (as long as pipe count is less than halved)

What would be different between doubling tbe pipe width vs number of pipes? (excluding inter lane operations that already had their own 512-bit pipe in Zen4)

Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#294

Post by dzaima »

camel-cdr wrote: post #293
dzaima wrote: post #181

Earlier quoted context omitted.

More importantly for the "2 cycles" question, Zen 4 can get one cycle latency for double-pumped 512-bit ops (for the ops where that's reasonable, i.e. basic integer/bitwise arith). Having all 512-bit pipes would still be a massive throughput improvement over Zen 4 (as long as pipe count is less than halved), if that is what Zen 5 actually does; things don't stop at 1 op/cycle. Though a rather important question with…

> Having all 512-bit pipes would still be a massive throughput improvement over Zen 4 (as long as pipe count is less than halved) What would be different between doubling tbe pipe width vs number of pipes? (excluding inter lane operations that already had their own 512-bit pipe in Zen4)

If those could be fed equally well (i.e. doubled decode width, reorder buffer sizes, register file ports), not much would be different, of course, but, from what I understand, that's significantly more expensive (given that the complexity of some of those things grow at O(n^2) or so (bypass network, connecting all pipes to all others? picking out the ops to run in a given cycle from the reorder buffer?), vs O(n) from just increasing width), so we probably won't be seeing 10 SIMD ports anytime soon.

Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#295

Post by camel-cdr »

dzaima wrote: post #294
camel-cdr wrote: post #293

Earlier quoted context omitted.

> Having all 512-bit pipes would still be a massive throughput improvement over Zen 4 (as long as pipe count is less than halved) What would be different between doubling tbe pipe width vs number of pipes? (excluding inter lane operations that already had their own 512-bit pipe in Zen4)

If those could be fed equally well (i.e. doubled decode width, reorder buffer sizes, register file ports), not much would be different, of course, but, from what I understand, that's significantly more expensive (given that the complexity of some of those things grow at O(n^2) or so (bypass network, connecting all pipes to all others? picking out the ops to run in a given cycle from the reorder buffer?), vs O(n) from…

You are probably right about the bypass network, but I don't see why ROB or decode would need to increase. Aren't avx512 instructions only "split" when already at a pipe in zen4? Also, my understanding was that the cpu can schedule avx2 instructions to the upper and lower part of the 512 wide pipes.

Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#296

Post by dzaima »

camel-cdr wrote: post #295
dzaima wrote: post #294

Earlier quoted context omitted.

If those could be fed equally well (i.e. doubled decode width, reorder buffer sizes, register file ports), not much would be different, of course, but, from what I understand, that's significantly more expensive (given that the complexity of some of those things grow at O(n^2) or so (bypass network, connecting all pipes to all others? picking out the ops to run in a given cycle from the reorder buffer?), vs O(n) from…

You are probably right about the bypass network, but I don't see why ROB or decode would need to increase. Aren't avx512 instructions only "split" when already at a pipe in zen4? Also, my understanding was that the cpu can schedule avx2 instructions to the upper and lower part of the 512 wide pipes.

Indeed Zen 4 splits uops just as it passes them to pipes, but Zen 4 is already doing that, adding more ports doesn't mean you can do it twice (without, like, making those ports 128-bit (thus not gaining any throughput), or making a new AVX-1024).

Allowing accessing separate parts of 512-bit pipes makes sense, but that still then needs separate ports for each half, otherwise there's nothing to schedule the other half to. uops.info data[0] shows that 256-bit shuffle throughput is indeed double that of 512-bit, but seemingly both still increment either the FP1 or FP2 port (these overlap the regular four ALU port numbers!) so the AVX2 shuffles still have two ports to taget.

So the mapping between Zen 4's (perf-counter-indicated) ports is rather unrelated from available execution units (not in any way a new concept, but still interesting). Which would seem to indicate that perhaps like "vaddps zmm; vpermd zmm" can manage 1/cycle, while "vaddps ymm; vaddps ymm; vpermd ymm; vpermd ymm" would fight for FP2 (for reference, vaddps uses either FP2 or FP3)? Fun.

[0]: https://uops.info/table.html?search=%22vpermd%20%22&cb_lat=o...

Re: AMD Unveils Ryzen 9000 CPUs for Desktop, Zen 5

#297

Post by brokencode »

icf80 wrote: post #50
ArtTimeInvestor wrote: post #15

Do all CPUs and GPUs these days involve components made by TSMC? If so, is this unique - that a whole industry of relies on one company?

wait till china invades

Good thing TSMC is getting billions of dollars of government subsidies to build fabs all around the world including in the US and Japan.
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