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Intel completely disables AVX-512 on Alder Lake after all

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Re: Intel completely disables AVX-512 on Alder Lake after all

#291
post #286

Earlier quoted context omitted.

That's one of the more useful ones! It's effectively a low-precision 4-component dot product feeding into an accumulator, which means it is a building block for larger dot products. Large dot products are very useful both in signal processing for FIR filters, as well as machine learning algorithms. The masking is just a bonus available on most AVX-512 operations and lets you do branchless if conditions. The majority…

Huh, TIL. Would you say that most AVX-512 instructions are then useful in such applications? Given Intel's history of inventing less than useful things (segmented memory, for example) I figured AVX-512 was mostly useless.

Well, segmented memory was a pain in the butt but was useful at the time -- not to mention _way_ less of a pain than bank-switched memory.

The applications that I mentioned wouldn't use all of AVX-512, but once you're familiar with vectorization it's not hard to tell what they are meant to be used for. CPU designers don't spend silicon on instructions that don't have a use, and AVX-512 does a lot to round out the vector instruction set to make it orthogonal and have less special cases.

The bad cases tend to be from instructions that are either too slow or are side effects of the general design. The horizontal add instructions in SSE4, for instance, would have been useful except that they were just as slow as manually doing the shuffles and adds yourself. AVX/AVX2 extended a bunch of SSE2-4 instructions to 256-bit by replicating them across lanes, which led to borderline useless forms like PALIGNR shifting within each 128-bit lane instead of across the entire vector. AVX-512 looks pretty good here though I have seen data about some mask operations being slow, not to mention the whole "slows down the whole chip" issue.

That having been said, it's hard to argue that AVX-512 _isn't_ mostly useless, if for no other reason than it being mostly unavailable. Baseline AVX-512 has a market penetration of only 5.6% in the Steam hardware survey and Intel shipping their latest chip without officially supporting it isn't going to help that. Only niche software can afford to use it right now.

Re: Intel completely disables AVX-512 on Alder Lake after all

#292

Earlier quoted context omitted.

If it's a random community member then this is just further evidence that the way Librem presented things and what they did confused people into thinking it actually had a practical purpose, when it was purely a way to rules-lawyer their way into getting RYF.

Hi, I'm the "random community member" who wrote that FAQ answer. Thanks for investigating how this works. Where is the file cpu_rec.py located? I can't find it. I will edit the FAQ answer to clarify that the DDR training blobs are being executed on an ARC core in the DDR controller, and not on the M4 core. I was going off what Angus Ainslie wrote ( https://puri.sm/posts/librem5-solving-the-first-fsf-ryf-hurd... ) tha…

cpu_rec: https://github.com/airbus-seclab/cpu_rec

> However, you seem to be unfairly criticizing Purism for obfuscation and legalisms, when it seems to me that Purism is just trying to comply with the FSF's rather arbitrary RYF rules

The question is why are they doing that? Why are they pandering to a program which ends up encouraging less free devices? RYF is completely broken and does not deliver what people think it does, and the FSF have shown zero interest in educating users about what it means and doesn't. It is a feel-good program that actually hurts the ecosystem behind the scenes. Why is Purism lending it legitimacy by attempting to get certification?

They should've done what bunnie did after Stallman showed up with that crazy "fuse the GPU off" idea: give up on this nonsense and focus on delivering a device as free as possible, instead of wasting engineering time pandering to a program that isn't helping anyone.

> It is not like Purism had any better options in terms of SoC's that it could have chosen for the Librem 5.

Indeed, and this is the crux of the problem: 100% libre modern hardware is impossible in the current world, but the FSF and people who buy in to their tactics keep pretending it is. That there is some magical line that denotes a device as "freedom-respecting" and they can just put things in that bucket and slap a sticker on it and sell it to all those freedom fanboys. This encourages further ignorance: users don't have to think about practicalities such as what security risks are actually present or what the lack of source code for some components might do to affect things they might practically want to do. They don't have to think about whether things are signed or validated, or how to verify that they are running software that is at the very least trusted to be a widely available build, or anything like that. They just see "no blobs in my filesystem!" "freedom!" and declare that device as a Friend of Free Software. And then they extrapolate from that a bunch of properties that are absolutely not implied, around privacy and security and more.

> It seems to me that Purism did the best that it could with an impossible situation, and if anybody should be criticized it is the FSF for not acknowledging how modern hardware actually works.

Purism did a decent job with the hardware; the RYF workaround development was completely unnecessary and just serves to legitimize the FSF, which, indeed, is the root of the problem.

> Another thing that I find problematic is your argument that 58 KB of DDR4 timer training blobs represent a security threat in the real world

Oh, they absolutely don't. In practice they don't; they also do not present any practical restriction on freedom. Even if the training code were open, I bet there isn't a single person who would ever modify it on a shipping device (especially one with soldered RAM). That's the kind of thing you need 6-figure test equipment to validate properly, and there is no reason to go mucking with it for any end user of the hardware. It existing as a blob causes zero reduction in practical freedom for users, because source code for it would only give you theoretical freedom that nobody wants or needs to exercise.

But you see, the entire FSF culture isn't about practicalities. That's the whole problem with it. It is about platonic ideals and philosophical arguments, and completely eschews looking at how real people are affected by software being open or closed. And from that point of view,

> and make the Librem 5 no different than an Apple device with an M1 processor

They indeed make it no different, because in both cases you're running blobs on boot, and you're in the same practical situation from an absolutist point of view, modulo the FSF's backdoor arguments.

> which is literally a black box.

How so? The i.MX8M is also a black box by that token; it's a pile of silicon. Sure, it may be (partially - those SoC programming manuals always have censored parts) documented, but it's not open hardware. You can't know what it does precisely. You can't prove the absence of a backdoor any more than you can with the M1.

> Forget the fact that the L5 is the first phone to have free/open source schematics

I have schematics for some of my M1 Macs. Sure, they leaked and were not willingly published... but in the end, I have them and can look things up in them. So for analysis/educational intents and purposes, I'm in a similar situation as you are with the L5.

(Of course it makes a difference in corporate goodwill that Purism published them deliberately; I'm just pointing out that you're limited to that aspect, since at the end of the day, we both have schematics for our devices, so we're both in the same situation as far as being able to understand them).

> and everything is running free/open source drivers.

We're working on that for the M1. You can run Linux on the M1 today with fully free/open source drivers for most critical parts of the hardware. This blog post has a table of hardware support and upstreaming status:

https://asahilinux.org/2021/12/progress-report-oct-nov-2021/

Looking up the Librem 5 devicetree in the upstream kernel, it seems it was submitted on Aug 21 2020. Aspen shipped in September 2019, so it took them about a year from shipping to upstreaming bring-up, and that's not considering internal prototypes and that the SoC was announced in mid 2018, so they had plenty of time to work on things internally.

I submitted upstream bring-up for the M1 Mac Mini with the device tree on Feb 4 2021, just 4 months after it was announced in Nov 2020. And that was working from scratch, on an unknown SoC, reverse engineering everything, having to make more intrusive patches to Linux because this SoC is quite "special", having to write our own pre-bootloader from scratch, etc. A year after release, we have a bunch more hardware working and on the way to upstreaming, including sound on the Mac Mini, I2C, SPI, NVMe, keyboard/trackpad on the laptops, USB and USB-C, power management, basic screen/display controller support, Wi-Fi (including on prior Macs going back to 2017), and support for 9 distinct hardware platforms including the just-launched M1 Pro and M1 Max models, which were already at feature parity a few weeks later. Given all that, I'd say we're doing a lot better with M1 upstream support with fully free drivers than Purism did, timeline-wise. And we didn't need a SoC programming manual. Maybe it's because we aren't wasting time trying to get RYF certification? :-)

Fun fact: the L5 and the M1 Macs use the same line of USB-PD controllers and share a driver, so it is very likely that some of our work on that front will benefit L5 users. The existing driver is very bare-bones and definitely needs more work.

> Think about how much code would be needed to initialize the cellular modem or WiFI and then run a TCP/IP stack to communicate with the outside world.

The M1 is in that situation too: Apple's bootloader is bare-bones and doesn't even support USB, let alone networking (by design). The Wi-Fi firmware is larger than the first-stage and second-stage bootloaders put together. The whole thing boots too fast to go around initializing Wi-Fi (just firmware upload and boot takes a few seconds on these modules...) and associating to a network and phoning home. And due to the SoC design, after boot, no proprietary code remains running on any secondary core with the ability to take over the system; all auxiliary cores running firmware are sandboxed behind IOMMUs, and the main CPU does not have the ability to run a secret supervisor/hypervisor under the OS (it can run a hypervisor but that cannot be done surreptitiously and silently; the guest knows).

And of course, given how Apple is constantly under attack by nation-state-sponsored entities like NSO, they have every incentive to fix security problems and build systems that are very difficult to compromise. To my knowledge, the L5 does not support any kind of secure boot (at least it is not implemented yet; the SoC itself might), nor does it make any attempt at being secure against physical access attacks (e.g. evil maid). The M1 does. I can install my own Linux bootloader, which requires entering my machine owner credentials, and know that nobody else can take over the device without wiping storage entirely via DFU mode, even if they have physical access, at least not without Apple's help (and even then there's ways of hardening that, but we're still working on the details). And I still don't have to delegate all my security to Apple; I can still use full disk encryption and know that even if they reboot the device to take over the boot process, they won't be able to get at my data.

This is not to say the M1 is a security panacea and the L5 is terrible. They each have their pros and cons. Some people might prefer one, some people might prefer the other. That's why we need to educate users about the realities of the devices they choose to purchase, instead of slapping meaningless "RYF" labels on them and discouraging nuanced discussion.

Re: Intel completely disables AVX-512 on Alder Lake after all

#293
post #286

Earlier quoted context omitted.

Huh, TIL. Would you say that most AVX-512 instructions are then useful in such applications? Given Intel's history of inventing less than useful things (segmented memory, for example) I figured AVX-512 was mostly useless.

Well, segmented memory was a pain in the butt but was useful at the time -- not to mention _way_ less of a pain than bank-switched memory. The applications that I mentioned wouldn't use all of AVX-512, but once you're familiar with vectorization it's not hard to tell what they are meant to be used for. CPU designers don't spend silicon on instructions that don't have a use, and AVX-512 does a lot to round out the vec…

Thanks for the info, this was insightful. :)

Re: Intel completely disables AVX-512 on Alder Lake after all

#294

Earlier quoted context omitted.

My 7700K (2017) got a similar downgrade in performance from the mitigations. Switched to AMD for the first time in my life, no regrets so far.

mitigations=off is IMHO a save thing to do on a single user desktop unless you have nation state level adversaries

I did not expect the “I don’t have anything important enough” excuse on HN.

You do not need to be a nation state to fall victim to sophisticated attacks. Most attacks nowadays are performed by bots indiscriminately blasting exploits to anything they can reach.

Even if state actors were the only ones capable of exploiting Spectre/Meltdown, you could still end up being collateral damage.

Infecting employees at their home computers and then spreading via USB/shared files to work computers is nothing new either.

Re: Intel completely disables AVX-512 on Alder Lake after all

#295

Earlier quoted context omitted.

I hear hardware vendors are scared shitless of running awful of other hardware vendor's patents. If they released their firmware, this would give other folks ammunitions to attack them in court. Personally, I don't care much about firmware being proprietary, if it cannot be used to meaningfully change the functionality of the chip . But I do care about the chip ultimately following a public specification. I want an I…

Unfortunately, from my understanding, hardware innovation seems to be on a trajectory whereby it is exactly going toward the case that most functionality is "soft" and thereby fundamental changes can be wrought through microcode. Just look at Nvidia's use of FALCON's. Hardware manufacturers seemingly WANT to be able to use the same piece of hardware for different jobs, and having blobs tooled to reconfigure it is the…

That’s the thing about microcoded machines: they’re fundamentally flexible. Even so, to be honest I don’t care too much about that. What I really want is a reliable, stable enough interface to the hardware.

Besides, there are other ways to get that flexibility. CPUs for instance have a very flexible ISA: even if they’re set in stone, we can use them for pretty much anything, the only real limitation being performance.

Now when I think about it, even if firmware can significantly change the functionality of a chip, I don’t care too much of it being proprietary. Not more than I care about fixed hardware being proprietary. It’s okay for a piece of hardware to have 3 or 10 different configurations, as long as (i) I can trust that each configuration works as advertised, and (ii) the ISA I got from each configuration is publicly documented.

There’s a practical reason for this wish: hardware is typically orders of magnitude more reliable than software. That’s mostly because buggy software is easily updated, while flawed hardware is often impossible to sell. CPU bugs do happen, but they’re sufficiently few and far between that when my programs behave unexpectedly, I can safely assume it’s the software’s fault.

I don’t want drivers any more, I want the hardware’s manual. https://caseymuratori.com/blog_0031

Re: Intel completely disables AVX-512 on Alder Lake after all

#296
post #219

Earlier quoted context omitted.

Hacking BIOS images isn't always that easy. Often they are signed (EFI Capsules) and the standard update utility in the BIOS menu will reject modified versions. I had to use a convoluted flashing process to make a trivial patch to a BIOS a few years back for this reason.

You mean, SOIC clip + flashrom?

That usually works, yes (modulo Boot Guard and electrical issues), but we're getting into less accessible methods, aren't we :)

In my case I managed to get it to work with some random vendor tools run from DOS, which bypassed the EFI flash subsystem. Definitely not a pleasant experience.

Re: Intel completely disables AVX-512 on Alder Lake after all

#297
post #270

Earlier quoted context omitted.

> According to the sources, users would need to disable E-cores I don't know the specificis of these CPUs, but it seems likely that _a sane design_ could allow heterogeneous CPU features within a single machine. For example, let's assume two CPU feature sets, E and P. E is a proper subset of P. Further, an E core will issue an "illegal instruction" exception when it encounters an instruction that is undefined on E an…

Actually, iirc the Apple M1 has that x86 memory model thing on P cores only. And macOS must then only schedule x86 processes on those.

It turned out that was inaccurate IIRC, and both have the TSO MSR bit.

Re: Intel completely disables AVX-512 on Alder Lake after all

#298

Stuff like this is why I plan to never buy Intel ever again. I always disliked Intel's strategy for market segmentation by disabling specific instructions, I much prefer AMD's strategy of segmenting just by speed and number of cores. It is really annoying that with Intel you can't run the same program on the server and on your desktop, it makes development and testing a huge pain.

Fair enough. I just bought a laptop with an Intel Core i7-1165G7.

The reason is I got tired of dealing with Ubuntu being unable to be installed in my AMD Ryzen 2500U.

Yes, even with the latest version using the latest kernel, and my last attempt to install it was a few days ago in 2022.

Last time I mentioned this issue about AMD in this forum I was downvoted, but I don't care, I am writing now this comment from a nice laptop, and I'm back in Linux again, so I am happy with this decision.

My point is: yes, AMD market segmentation is better, and I wish them the best. But for my particular use case: Windows is not enough, and I require the machine to work in Linux, therefore Intel is a must.

Re: Intel completely disables AVX-512 on Alder Lake after all

#299

Earlier quoted context omitted.

My 7700K (2017) got a similar downgrade in performance from the mitigations. Switched to AMD for the first time in my life, no regrets so far.

mitigations=off is IMHO a save thing to do on a single user desktop unless you have nation state level adversaries

There are Spectre/Meltdown exploits done in JavaScript, on the browser. You do NOT want to turn off mitigations unless you're in a Faraday cage.

Re: Intel completely disables AVX-512 on Alder Lake after all

#300
post #144

Earlier quoted context omitted.

It worked for one SKU at launch and by disabling up to 50% of the cores of the others. Calling that a working feature is a bit of a stretch already.

That was before Ice Lake, where it had a very decent performance (just downclocking 10%) and then on Rocket Lake it didn't even downclock [0]. But the thing that stuck in our collective mind was that "it's bad because it downclocks". And seeing the RKL numbers, which are new to me (I had only read de Ice Lake numbers back in 2020) it wasn't even 14nm's fault, just an implementation issue which Intel eventually worked…

> That was before Ice Lake

My comment was about Alder Lake, where only P-cores even have AVX-512 units.

The i9 has 8 P-cores and 8 E-cores and users need to disable the 8 E-cores to use AVX-512. That's 50% of the cores gone for very niche use cases.

Considering that the PS3 emulator only got ~10% better performance on the highest end, it'd be better to simply get an 11th gen high-end part instead of a lower end 12th gen CPU for that use case anyway, so I really don't understand what the fuss is about.

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