Earlier quoted context omitted.
Even in VLIW, DRAM fetches are slow, instructions have variable latency and write-before-retire register collisions require renaming. Itanium would have gotten there at some point. OO isn't an optional feature for high performance systems and that was clear even in the 90's.
If you have that what's the VLIW getting you?
ld r1, [r2 + 10]
st [r3 + 4], r4
And then consider things like speculative execution.